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Support for SystemC
Support for Verilog 2001
Third
party tools integrated with FinSim
Verilog 2001 features supported todate by all FinSim simulators.
For details regarding these features please consult "IEEE 1364-2001 Verilog LRM", as well as Stuart Sutherland's "Verilog 2001: A Guide to New Features of the Verilog Hardware Description Language". The numbering used is from Stuart Sutherland's book.
1. Combined port and data declaration
2. ANSI C style module declarations
3. Module port parameter lists
4. ANSI C style UDP declarations
5. Variable initial value at declaration
6. ANSI C style task/function declarations
9. Constant Functions
10. Comma separated sensitivity list
11. Combinational logic sensitivity @(*)
12. Implicit net declarations for continuous assignments
13. Disabling of implicit net declarations for continuous assignments
14. Variable vector part selects
15. Multidimensional arrays
16. Arrays of net and real data types. (Arrays of reals only in compile mode)
17. Array bit and part selects. Non-blocking assignments to bit or part selects are supported only in compiled mode.
18. Signed reg, net, and port declarations
19. signed based integer numbers
20. signed functions
21. sign conversion system functions
22. Arithmetic Shift Operator
23. Assignment width extension past 32 bits
24. Power Operator
25. Attributes
26. Sized and typed parameter constants
27. Explicit in-line parameter redefinition
28. Fixed local parameters
30. Extended number of open files: $fopen with single and multiple channel descriptors
31 Enhanced file I/O (Not in interpreted mode, only in compiled mode!): $fgetc, $fgets, $fscanf (%z not supported)
33. Enhanced Invocation Option Testing: $value$plusargs
34. Enhanced conditional compilation: 'ifndef and 'elsif compiler directives
36. Generate blocks
38. On-detect pulse error propagation:
- pulsestyle_onevent
- pulsestyle_ondetect
39. Negative pulse detection:
- showcancelled
- noshowcancelled
40. Enhanced input timing checks:
- $setup
- $hold
- $setuphold
- $skew
- $recovery
- $period
- $width
41. Negative input timing constraints
- $setuphold
- $recrem