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Translating a FinSimMath description of FFT to SystemC


FinSimMath is an extension of Verilog that provides high level mathematical capabilities.

By supporting both high level matehmatical descriptions and the Verilog capabilities, FinSimMath provides
for the implementation of mathematical algorithms into circuits what Verilog and VHDL brought to implementing
RTL descriptions into gate-level descriptions, namely a huge productivity increase at all steps of the design process.

The capability of translating FinSimMath to SystemC is important because it helps integrate FinSimMath into
SystemC development environments and provides a way to use the Synthesis capabilities available for SystemC.

The capability to co-simulate FinSimMath and SystemC furhter helps to integrate FinSimMath into SystemC
environments and makes it possible to translate FinSimMath to SystemC for simulation purposes and not only for synthesis purposes.

This example works on FinSim 10_04_92s and subsequent versions.
It translates a FinSimMath description of FFT to SystemC for synthesis purposes and to SystemC/FinSimMath co-simulation for simulation purposes.

The original FinSimMath description of the FFT is in the file vpfft.v
The command to translate vpfft.v into SystemC and FinSimMath is 

 finvc +gen_sysc vpfft.v

The generated SystemC files are fin_sysc.cpp which includes fin_sysc_top.h.
The file fin_sysc.cpp contains the compiler directive #define SIM.
For synthesis purposes one should comment out this directive.
For synthesis, the translation is done in terms of functions performing arithmetic operations.
The operations can be on of various object types (cartesian, polar, real, integer, variable precision) and formats (floating or fixed point).
The FinSimMath system functions and tasks are also translated for synthesis purposes into SystemC function.

The name of the functions indicate the actual functionality.
These functions must already be supported by the synthesis environment.

For simulation purposes the directive #define SIM must be present. The code in the file fin_sysc.cpp will co-simulate with the code in the file fin_sysc.v.
The commands to perform the co-simulations are: 

finvc +FM -a -systemc fin_sysc.cpp fin_sysc.v
finbuild
TOP.sim

The co-simulation SystemC/FinSimMath provides several benefits:
1) It ensures that the simulation executes very fast.
This is due to the fact that the arithmetic operations and other basic functions such as trigonometric functions
are simulated at the high mathematical level and yet bit-accurate.
The bit accuracy is made possible by FinSimMath's variable precision capabilities.
2) It allows stimulus to be generated using high level bit-accurate mathematical system functions, such as $VpSin.
3) It allows simulation results to be processed and displayed using high level system tasks and functions such as $VpFft and $Flot.
4) It allows the synthesized design to produce the same simulation results as the high level FinSimMath description.

The original FinSimMath description of the FFT is presented below: 

 module top;
module top;
`include "finsimmath.h"
   parameter real srate = 200.000000;
   parameter SIZE = 1024;
   parameter WIDTH = 140;
   real y[0:2][0:SIZE-1];

   VpFComplex inSpectrum[0:SIZE-1];
   VpFCartesian cart;
   VpFPolar polar;
   VpDescriptor d1;
   integer i, j, k, l, n, le, wptr, windex, logSize;
   real    sz, rlogsz, delta, tmpr, step;
   VpReg [0:63] tmpvp1, tmpvp2;
  
   VpReg [0:WIDTH-1] MywReV[0:SIZE/2-1];
   VpReg [0:WIDTH-1] MywImV[0:SIZE/2-1];
   VpReg [0:WIDTH-1] MywIReV[0:SIZE/2-1];
   VpReg [0:WIDTH-1] MywIImV[0:SIZE/2-1];
   VpReg [0:WIDTH-1] MyRe[0:SIZE-1];
   VpReg [0:WIDTH-1] MyIm[0:SIZE-1];
   VpReg [0:WIDTH-1]  wrecRe, wrecIm, wRe, wIm, wtemp, uRe, 
     uIm, scale, tempRe, tempIm, tmp1Re, tmp1Im, tmp2Re, tmp2Im, tmRe, tmIm, arg;

initial begin
   $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT,
                        `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, 
                        `SATURATION+`WARNING, 1);
   $VpAssocDescrToData(tmpvp1,  d1);
   $VpAssocDescrToData(tmpvp2,  d1);
   $VpAssocDescrToData(MyRe,  d1);
   $VpAssocDescrToData(MyIm,  d1);
   $VpAssocDescrToData(MywReV,  d1);
   $VpAssocDescrToData(MywImV,  d1);
   $VpAssocDescrToData(MywIReV,  d1);
   $VpAssocDescrToData(MywIImV,  d1);
   $VpAssocDescrToData(wrecRe,  d1);
   $VpAssocDescrToData(wrecIm,  d1);
   $VpAssocDescrToData(wRe,  d1);
   $VpAssocDescrToData(wIm,  d1);
   $VpAssocDescrToData(uRe,  d1);
   $VpAssocDescrToData(uIm,  d1);
   $VpAssocDescrToData(tempRe,  d1);
   $VpAssocDescrToData(tempIm,  d1);
   $VpAssocDescrToData(tmRe,  d1);
   $VpAssocDescrToData(tmIm,  d1);
   $VpAssocDescrToData(tmp1Re,  d1);
   $VpAssocDescrToData(tmp1Im,  d1);
   $VpAssocDescrToData(tmp2Re,  d1);
   $VpAssocDescrToData(tmp2Im,  d1);
   $VpAssocDescrToData(scale,  d1);
   $VpAssocDescrToData(arg,  d1);
   $VpAssocDescrToData(wtemp,  d1);

   //$display(" load Re and Im \n");
   delta = $Pi;
   delta = 2*delta;
   
   delta = delta/SIZE;
   for (j = 0; j < SIZE; j++)
     begin
	tmpr = delta*j;
	tmpr = 51.20000*tmpr;
	MyIm[j] = 0;
	
        MyRe[j] = $VpSin(tmpr);
     end
     $InitM(inSpectrum, MyRe[$I1], 0);
     $VpFft(inSpectrum, 0, SIZE-1);
     $PrintM(inSpectrum, "%e");
     for (j = 0; j < (SIZE/2); j = j + 1)
       begin
         polar = inSpectrum[j];
         y[0][j] = polar.Mag;
       end
     $PrintM(y, "%e");
     step = srate/(SIZE/2);
     $Flot("Spectrum_High_level.html", 1, step, "Spectrum", "frequency (GHz)", "Amplitude ", 0, SIZE/2-1, y, "inSpectrum");

   sz = SIZE;
   rlogsz = $VpLog(2.0, sz);
   logSize = rlogsz;

  //$display("Compute wRe and wIm\n");
   n = SIZE;
   le = n /2;
   arg = 4.0*$VpAtan(1.0)/le;
   wrecRe = $VpCos(arg);
   wRe = wrecRe;
   wrecIm = -$VpSin(arg);
   
   wIm = wrecIm;
   for (j = 0; j < le - 1; j++)
     begin
       MywReV[j] = wrecRe;
       MywImV[j] = wrecIm;
	tmpvp1 =  wrecRe * wRe;
	tmpvp2 = wrecIm * wIm;
	wtemp = tmpvp1 - tmpvp2;
	tmpvp1 = wrecRe * wIm;
	tmpvp2 = wrecIm * wRe;
	wrecIm = tmpvp1 + tmpvp2;
       wrecRe = wtemp;
     end 

  //$display("Perform FFT \n");
  le = n;
  windex = 1;
       
  for (l = 0; l < logSize; l = l + 1) begin
    le = le / 2;
    for (i = 0; i < n; i = i + 2 * le) begin
      tmp1Re = MyRe[i];
      tmp1Im = MyIm[i];
      tmp2Re = MyRe[i+le];
      tmp2Im = MyIm[i+le];

      MyRe[i] = tmp1Re + tmp2Re;
      MyIm[i] = tmp1Im + tmp2Im;
      MyRe[i+le] = tmp1Re - tmp2Re;
      MyIm[i+le] = tmp1Im - tmp2Im;
    end
    wptr = windex - 1;
    for (j = 1; j < le; j = j + 1) begin
      uRe = MywReV[wptr];
      uIm = MywImV[wptr];
      for (i = j; i < n; i = i + 2 * le) begin
	tmp1Re = MyRe[i];
	tmp1Im = MyIm[i];
	tmp2Re = MyRe[i+le];
	tmp2Im = MyIm[i+le];

	MyRe[i] = tmp1Re + tmp2Re;
	MyIm[i] = tmp1Im + tmp2Im;
	tmRe = tmp1Re - tmp2Re;
	tmIm = tmp1Im - tmp2Im;

	 tmpvp1 =  tmRe * uRe;
	 tmpvp2 = tmIm * uIm;
         MyRe[i+le] = tmpvp1 - tmpvp2;
	 tmpvp1 = tmRe * uIm;
	 tmpvp2 = tmIm * uRe;
	 MyIm[i+le] = tmpvp1 + tmpvp2;
      end
      wptr = wptr + windex;
    end
    windex = windex * 2;
  end

  //$display("Rearange data\n");
  j = 0;
  for (i = 1; i < (n-1); i = i + 1) begin
    k = n/2;
    while (k <= j) begin
      j = j - k;
      k = k / 2;
    end
    j = j + k;
    if (i < j) begin
      tempRe = MyRe[j];
      tempIm = MyIm[j];
      MyRe[j] = MyRe[i];
      MyIm[j] = MyIm[i];
      MyRe[i] = tempRe;
      MyIm[i] = tempIm;
    end	
  end
   for (j = 0; j < SIZE/2; j = j + 1)
     begin
	cart.Re  = MyRe[j];
	cart.Im = MyIm[j];
	polar = cart;
        y[0][j] = polar.Mag;
     end
   step = srate/(SIZE/2);
   $Flot("Spectrum_detailed.html", 1, step, "Spectrum", "frequency (GHz)", "Amplitude ", 0, SIZE/2-1, y, "inSpectrum");

   $display("Simulation Finished");

end /*initial*/
endmodule

The generated SystemC description resides in the file fin_sysc.cpp, which includes the generated file fin_sysc_top.h.

These files are obtained by executing: finvc +gen_sysc vpfft.v, where vpfft.v is the name of the original FinSimMath description of FFT.

The generated file fin_sysc_top.h is presented below: 

 
sc_int<32> fin__tmp_simplify_all3 ;
sc_int<32> fin__tmp_simplify_all2 ;
sc_int<32> fin__tmp_simplify_all1 ;
sc_int<32> fin__tmp_simplify_all0 ;
sc_int<32> fin__tmp_int9 ;
sc_int<32> fin__tmp_int8 ;
sc_int<32> fin__tmp_int7 ;
sc_int<32> fin__tmp_int6 ;
sc_int<32> fin__tmp_int5 ;
sc_int<32> fin__tmp_int4 ;
sc_int<32> fin__tmp_int3 ;
sc_int<32> fin__tmp_int2 ;
sc_int<32> fin__tmp_int1 ;
sc_int<32> fin__tmp_int0 ;
double  fin__tmp_real0;
double  fin__tmp_sysf1;
double  fin__tmp_sysf0;
sc_int<32> fin__tmp_idx9 ;
sc_int<32> fin__tmp_idx8 ;
sc_int<32> fin__tmp_idx7 ;
sc_int<32> fin__tmp_idx6 ;
sc_int<32> fin__tmp_idx5 ;
sc_int<32> fin__tmp_idx4 ;
sc_int<32> fin__tmp_idx3 ;
sc_int<32> fin__tmp_idx2 ;
sc_int<32> fin__tmp_idx1 ;
sc_int<32> fin__tmp_idx0 ;
sc_logic fin__tmp_logical11;
sc_logic fin__tmp_logical10;
sc_logic fin__tmp_logical9;
sc_logic fin__tmp_logical8;
sc_logic fin__tmp_logical7;
sc_logic fin__tmp_logical6;
sc_logic fin__tmp_logical5;
sc_logic fin__tmp_logical4;
sc_logic fin__tmp_logical3;
sc_logic fin__tmp_logical2;
sc_logic fin__tmp_logical1;
sc_logic fin__tmp_logical0;
sc_logic fin_tmp_for_cond_8;
sc_logic fin_tmp_cond_if_0;
sc_logic fin_tmp_cond_while_0;
sc_logic fin_tmp_for_cond_7;
sc_logic fin_tmp_for_cond_6;
sc_logic fin_tmp_for_cond_5;
sc_logic fin_tmp_for_cond_4;
sc_logic fin_tmp_for_cond_3;
sc_logic fin_tmp_for_cond_2;
sc_logic fin_tmp_for_cond_1;
sc_logic fin_tmp_for_cond_0;
double  Fin__I [2];
sc_lv<96>  Fin__EM;
double  inf;
#define  srate  200.000000
#define  SIZE (sc_int<32>)1024
#define  WIDTH (sc_int<32>)140
double  y [3072];
double  inSpectrum [2048];
double  cart [2];
double  polar [2];
sc_lv<2> d1;
sc_int<32> i ;
sc_int<32> j ;
sc_int<32> k ;
sc_int<32> l ;
sc_int<32> n ;
sc_int<32> le ;
sc_int<32> wptr ;
sc_int<32> windex ;
sc_int<32> logSize ;
double  sz;
double  rlogsz;
double  delta;
double  tmpr;
double  step;
sc_lv<24>  tmpvp1;
sc_lv<24>  tmpvp2;
sc_lv<24>  MywReV[512];
sc_lv<24>  MywImV[512];
sc_lv<24>  MywIReV[512];
sc_lv<24>  MywIImV[512];
sc_lv<24>  MyRe[1024];
sc_lv<24>  MyIm[1024];
sc_lv<24>  wrecRe;
sc_lv<24>  wrecIm;
sc_lv<24>  wRe;
sc_lv<24>  wIm;
sc_lv<24>  wtemp;
sc_lv<24>  uRe;
sc_lv<24>  uIm;
sc_lv<24>  scale;
sc_lv<24>  tempRe;
sc_lv<24>  tempIm;
sc_lv<24>  tmp1Re;
sc_lv<24>  tmp1Im;
sc_lv<24>  tmp2Re;
sc_lv<24>  tmp2Im;
sc_lv<24>  tmRe;
sc_lv<24>  tmIm;
sc_lv<24>  arg;

The generated SystemC file, fin_sysc.cpp, is presented below: 

 
#define SIM
#include 
#include 
#include "/home/alec/finsim/test_rel/10_08_100s/include/fin_systemc.h"
extern "C" {
#include "/home/alec/finsim/test_rel/10_08_100s/include/simsc2fn.h"
#define HIDE 1
#include "/home/alec/finsim/test_rel/10_08_100s/include/finsysc.h"
#undef HIDE
}
sc_lv<64> finVpRealToBits(double in)
{
unsigned long long *l = (unsigned long long *) ∈
return *l;
}

sc_lv<64> finScRealToBits(double in)
{
unsigned long long *l = (unsigned long long *) ∈
return *l << 32 | *l >> 32;
}

double finScBitsToReal(sc_lv<64> in)
{
double result;
unsigned long a, b;
a = in.get_word(0);
b = in.get_word(1);
memcpy(((unsigned char*) &result), &b, 4);
memcpy(((unsigned char*) &result)+4, &a, 4);
return result;
}

bool finLogicToBool(sc_logic in)
{
  switch (in.m_val) {
case H:
return 1;
break;
case L:
return 0;
break;
case X:
return 0;
break;
case Z:
return 0;
break;
  }
}
int finScBitsToInteger(sc_lv<64> in)
{
int result;
unsigned long a, b;
a = in.get_word(0);
memcpy(&result, &a, 4);
return result;
}

#define FSTLOGSIZE 5
#define PTR_WIDTH 8
#define FIN_USER_ERROR 2
#define finPrint printf
#define finExit exit
#define FSTVPGETDESCRIPTOR(opP, tmpAbP)\
   memcpy((char *) &tmpAbP, (char *) &((opP)->abP[(opP)->lastAbNum + 1].a), PTR_WIDTH); \
   if (tmpAbP == NULL) { \
      finPrint("Error in referencing variable precision object: it has no descriptor associated to it\n"); \
     finExit(FIN_USER_ERROR); \
   }
#define FSTVPSETDESCRIPTOR(opP, tmpAbP) \
  memcpy(&((opP)->abP[opP->lastAbNum + 1].a), &tmpAbP, PTR_WIDTH); 
#define FSTVPGETLASTBITNUM(val)\
      (((val) == 0) ? 0 : (((val)-1) % 32)) 
#define FSTVPGETLASTABNUM(val) \
  (((((val) >> FSTLOGSIZE)<< FSTLOGSIZE) != (val)) ?\
      ((val) >> FSTLOGSIZE) : (((val) >> FSTLOGSIZE)-1)) 
#define FSTSETNRBITS(opP, nrBits)\
  (opP)->lastBitNumMod = FSTVPGETLASTBITNUM((nrBits));\
  (opP)->lastAbNum = FSTVPGETLASTABNUM((nrBits)); 
#define SIM_SIG_MEMP(sigP)  (sigP)->misc.memP 
#define FSTVPGETMIDX(start1, end1, start2, end2, sz2, i, k)\
(sz2*((start1 > end1) ? (i-end1) : (i - start1)) + \
 ((start2 > end2) ? (k-end2) : (k - start2))) 
#define FSTVPMGET(op1MP, l1P, idx1, start11, end11, start12, end12, sz11,\
                    msb1, lsb1, i, k, tmp1Re, size)\
   idx1 = FSTVPGETMIDX(start11, end11, start12, end12, sz11, i, k); \
   if (l1P) {\
     assert(0); \
   }\
   else {\
     simVpGet(op1MP, idx1, &tmp1Re, msb1, lsb1, size);\
   } 
#define FSTVPMPLACE(op1MP, l1P, idx1, start11, end11, start12, end12, sz11,\
                    msb1, lsb1, i, k, tmp1Re, size)\
   idx1 = FSTVPGETMIDX(start11, end11, start12, end12, sz11, i, k); \
   if (l1P) {\
     assert(0); \
   }\
   else {\
     simVpPlace(op1MP, idx1, &tmp1Re, msb1, lsb1, size);\
   } 
   int fin__i 
;   int fin__j 
;   int fin__k 
;void finReadInt1(simSignalPT signalP, int startSc, int startVer, int numWords, int size, sc_int<32> *result)

{  char *memPtr;
  int i;
  memPtr = signalP->misc.memP->p.memoryP;
  for (i = 0; i < numWords; i++) {
    fstBundleT tmp;
   fstAbT ab;
   tmp.abP = &ab;
   tmp.offset = 0;
   FSTSETNRBITS(&tmp, 32);
    simVpGet_i(memPtr, startVer+i, &tmp, 0, size-1);
    result[startSc+i] = tmp.abP->a;
  }
}
void finWriteInt1(sc_int<32> *val, simSignalPT signalP, int startSc, int startVer, int numWords, int size)
{  char *memPtr;
  int i;
  memPtr = signalP->misc.memP->p.memoryP
;  for (i = 0; i < numWords; i++) {
    fstBundleT tmp;
    fstAbT ab;
    tmp.abP = &ab;
    tmp.offset = 0;
    FSTSETNRBITS(&tmp, 32);
    tmp.abP->a = val[startSc+i];
    tmp.abP->b = 0;
    simVpPlace_i(memPtr, startVer+i, &tmp, 0, size-1);
  }
}
void waitDelta1(sc_signal &id)
{
  id = (id == sc_logic_X || id == sc_logic_Z) ? sc_logic_1 : ~(id.read());
  wait();
}

class vvpDelta1 : public sc_foreign_module {
public: 
sc_in iv;
sc_out ov;
vvpDelta1(sc_module_name nm) : sc_foreign_module(nm, "vvpDelta1"), iv("iv"), ov("ov") {}
~vvpDelta1() {}
};
sc_signal od1, id1;
sc_signal > R1_op1;
sc_signal > R1_op2;
sc_signal R1_iv, R1_ov;

class I1_c : public sc_foreign_module {
public:
sc_in > op1;
sc_out > op2;
sc_in iv;
sc_out ov;
I1_c(sc_module_name nm) :
sc_foreign_module(nm, "I1_c"), op1("op1"), op2("op2"), iv("iv"), ov("ov") {}
 ~I1_c() {}
};

void waitDelta2(sc_signal &id)
{
  id = (id == sc_logic_X || id == sc_logic_Z) ? sc_logic_1 : ~(id.read());
  wait();
}

class vvpDelta2 : public sc_foreign_module {
public: 
sc_in iv;
sc_out ov;
vvpDelta2(sc_module_name nm) : sc_foreign_module(nm, "vvpDelta2"), iv("iv"), ov("ov") {}
~vvpDelta2() {}
};
sc_signal od2, id2;
sc_signal > R2_op2;
sc_signal R2_iv, R2_ov;

class Pi_2_c : public sc_foreign_module {
public:
sc_out > op1;
sc_in iv;
sc_out ov;
Pi_2_c(sc_module_name nm) :
sc_foreign_module(nm, "Pi_2_c"), op1("op1"), iv("iv"), ov("ov") {}
 ~Pi_2_c() {}
};

sc_signal > R3_op1;
sc_signal > R3_op2;
sc_signal R3_iv, R3_ov;

class I3_c : public sc_foreign_module {
public:
sc_in > op1;
sc_out > op2;
sc_in iv;
sc_out ov;
I3_c(sc_module_name nm) :
sc_foreign_module(nm, "I3_c"), op1("op1"), op2("op2"), iv("iv"), ov("ov") {}
 ~I3_c() {}
};

sc_signal > R4_op1;
sc_signal > R4_op2;
sc_signal R4_iv, R4_ov;

class I4_c : public sc_foreign_module {
public:
sc_in > op1;
sc_out > op2;
sc_in iv;
sc_out ov;
I4_c(sc_module_name nm) :
sc_foreign_module(nm, "I4_c"), op1("op1"), op2("op2"), iv("iv"), ov("ov") {}
 ~I4_c() {}
};

sc_signal > R5_address1;
sc_signal > R5_address2;
sc_signal R5_iv, R5_ov;

class I5_c : public sc_foreign_module {
public:
sc_out > address1;
sc_out > address2;
sc_in iv;
sc_out ov;
I5_c(sc_module_name nm) :
sc_foreign_module(nm, "I5_c"), address1("address1"), address2("address2"), iv("iv"), ov("ov") {}
 ~I5_c() {}
};

#ifdef SIM
void copySyscArrayToVer_24_scalar_vp_1024(const sc_lv<64> *address, int startSc, int startVer, int numWords, sc_lv<24> *scArr)
{
int i, nr, msb, lsb, bcnt, idx;
simSignalPT signalP;
char *opMP;fstValueT tmpVal;
fstBundleT tmpBundle;
fstAbT tmpAb[3099];
fstAbPT tmp1AbP;
unsigned long long addr = (((unsigned long long) address->m_ctrl[0]) << 32 | address->m_data[0]);
memcpy(&signalP, &addr, sizeof(unsigned long long));
msb = SIM_SIG_MEMP(signalP)->msb1d;
lsb = SIM_SIG_MEMP(signalP)->lsb1d;
opMP = signalP->misc.memP->p.memoryP;
bcnt = SIM_SIG_MEMP(signalP)->bCnt;
tmpVal.bundleP = &tmpBundle;
tmpBundle.abP = tmpAb;
nr = bcnt*4;
FSTSETNRBITS(&tmpBundle, nr);
FSTVPMGET(opMP, NULL, idx, 0, numWords-1, 0, 0, 1, msb, lsb, 0, 0, tmpBundle, bcnt);
nr = nr - 32;
FSTSETNRBITS(&tmpBundle, nr);
FSTVPGETDESCRIPTOR(&tmpBundle, tmp1AbP);
nr = tmp1AbP[0].a + tmp1AbP[0].b;
FSTSETNRBITS(&tmpBundle, nr);
FSTVPSETDESCRIPTOR((&tmpBundle), tmp1AbP);
for (i = startSc; i <= numWords+startSc-1; i++) {
sc_lv<24> *scVal = scArr+i;
syscConvertSc2Fn_lv_b(scVal->m_data, scVal->m_ctrl, nr, &tmpVal);
FSTVPMPLACE(opMP, NULL, idx, 0, numWords-1, 0, 0, 1, msb, lsb, i-startSc+startVer, 0, tmpBundle, bcnt);
}
}
#endif
#ifdef SIM
void copyVerArrayToSysc_64_real(const sc_lv<64> *address, int startSc, int startVer, int numWords, double *scArr)
{
simSignalPT signalP;
unsigned long long addr = (((unsigned long long) address->m_ctrl[0]) << 32 | address->m_data[0]);
memcpy(&signalP, &addr, sizeof(unsigned long long));
  finReadReal1(signalP, startSc, startVer, numWords, 2048, scArr);
}
#endif
sc_signal > R6_address1;
sc_signal > R6_op2;
sc_signal > R6_op3;
sc_signal R6_iv, R6_ov;

class VpFft_fcomplex_2_2048_scalar_integer_0_1_scalar_integer_0_1_6_c : public sc_foreign_module {
public:
sc_out > address1;
sc_in > op2;
sc_in > op3;
sc_in iv;
sc_out ov;
VpFft_fcomplex_2_2048_scalar_integer_0_1_scalar_integer_0_1_6_c(sc_module_name nm) :
sc_foreign_module(nm, "VpFft_fcomplex_2_2048_scalar_integer_0_1_scalar_integer_0_1_6_c"), address1("address1"), op2("op2"), op3("op3"), iv("iv"), ov("ov") {}
 ~VpFft_fcomplex_2_2048_scalar_integer_0_1_scalar_integer_0_1_6_c() {}
};

#ifdef SIM
void copySyscArrayToVer_64_fcomplex_2048(const sc_lv<64> *address, int startSc, int startVer, int numWords, double *scArr)
{
simSignalPT signalP;
unsigned long long addr = (((unsigned long long) address->m_ctrl[0]) << 32 | address->m_data[0]);
memcpy(&signalP, &addr, sizeof(unsigned long long));
  finWriteReal1(scArr, signalP, startSc, startVer, numWords, 2048);
}
#endif
sc_signal > R8_address1;
sc_signal R8_iv, R8_ov;

class I8_c : public sc_foreign_module {
public:
sc_out > address1;
sc_in iv;
sc_out ov;
I8_c(sc_module_name nm) :
sc_foreign_module(nm, "I8_c"), address1("address1"), iv("iv"), ov("ov") {}
 ~I8_c() {}
};

sc_signal > R9_address1;
sc_signal > R9_address2;
sc_signal R9_iv, R9_ov;

class I9_c : public sc_foreign_module {
public:
sc_out > address1;
sc_out > address2;
sc_in iv;
sc_out ov;
I9_c(sc_module_name nm) :
sc_foreign_module(nm, "I9_c"), address1("address1"), address2("address2"), iv("iv"), ov("ov") {}
 ~I9_c() {}
};

sc_signal > R11_address1;
sc_signal R11_iv, R11_ov;

class I11_c : public sc_foreign_module {
public:
sc_out > address1;
sc_in iv;
sc_out ov;
I11_c(sc_module_name nm) :
sc_foreign_module(nm, "I11_c"), address1("address1"), iv("iv"), ov("ov") {}
 ~I11_c() {}
};

#ifdef SIM
void copySyscArrayToVer_64_scalar_real_3072(const sc_lv<64> *address, int startSc, int startVer, int numWords, double *scArr)
{
simSignalPT signalP;
unsigned long long addr = (((unsigned long long) address->m_ctrl[0]) << 32 | address->m_data[0]);
memcpy(&signalP, &addr, sizeof(unsigned long long));
  finWriteReal1(scArr, signalP, startSc, startVer, numWords, 3072);
}
#endif
sc_signal > R12_op1;
sc_signal > R12_op2;
sc_signal > R12_op3;
sc_signal > R12_op4;
sc_signal > R12_op5;
sc_signal > R12_op6;
sc_signal > R12_op7;
sc_signal > R12_op8;
sc_signal > R12_address9;
sc_signal > R12_op10;
sc_signal R12_iv, R12_ov;

class I12_c : public sc_foreign_module {
public:
sc_in > op1;
sc_in > op2;
sc_in > op3;
sc_in > op4;
sc_in > op5;
sc_in > op6;
sc_in > op7;
sc_in > op8;
sc_out > address9;
sc_in > op10;
sc_in iv;
sc_out ov;
I12_c(sc_module_name nm) :
sc_foreign_module(nm, "I12_c"), op1("op1"), op2("op2"), op3("op3"), op4("op4"), op5("op5"), op6("op6"), op7("op7"), op8("op8"), address9("address9"), op10("op10"), iv("iv"), ov("ov") {}
 ~I12_c() {}
};

sc_lv<192> vpNumberToBits_192(const char *val)
{
sc_lv<192> lv;
int bitsRemaining = 192, idx = 0;
for (int i = 0; i < 6; ++i) {
unsigned a = 0, b = 0;
for (int j = (32 < bitsRemaining ? 31 : bitsRemaining-1); j >=0; --j) {
switch (val[idx]) {;
case '0': break;
case '1': a |= (0x1 << j); break;
case 'X': case 'x': a |= (0x1 << j); break;
case 'Z': case 'z': a |= (0x1 << j); b |= (0x1 << j); break;
default: assert(0); break;
}
idx++;
}
bitsRemaining -= 32;
lv.set_word(6-1-i, (unsigned long) a);
lv.set_cword(6-1-i, (unsigned long) b);
}
return lv;
}
sc_lv<64> vpNumberToBits_64(const char *val)
{
sc_lv<64> lv;
int bitsRemaining = 64, idx = 0;
for (int i = 0; i < 2; ++i) {
unsigned a = 0, b = 0;
for (int j = (32 < bitsRemaining ? 31 : bitsRemaining-1); j >=0; --j) {
switch (val[idx]) {;
case '0': break;
case '1': a |= (0x1 << j); break;
case 'X': case 'x': a |= (0x1 << j); break;
case 'Z': case 'z': a |= (0x1 << j); b |= (0x1 << j); break;
default: assert(0); break;
}
idx++;
}
bitsRemaining -= 32;
lv.set_word(2-1-i, (unsigned long) a);
lv.set_cword(2-1-i, (unsigned long) b);
}
return lv;
}
sc_lv<120> vpNumberToBits_120(const char *val)
{
sc_lv<120> lv;
int bitsRemaining = 120, idx = 0;
for (int i = 0; i < 4; ++i) {
unsigned a = 0, b = 0;
for (int j = (32 < bitsRemaining ? 31 : bitsRemaining-1); j >=0; --j) {
switch (val[idx]) {;
case '0': break;
case '1': a |= (0x1 << j); break;
case 'X': case 'x': a |= (0x1 << j); break;
case 'Z': case 'z': a |= (0x1 << j); b |= (0x1 << j); break;
default: assert(0); break;
}
idx++;
}
bitsRemaining -= 32;
lv.set_word(4-1-i, (unsigned long) a);
lv.set_cword(4-1-i, (unsigned long) b);
}
return lv;
}
sc_lv<80> vpNumberToBits_80(const char *val)
{
sc_lv<80> lv;
int bitsRemaining = 80, idx = 0;
for (int i = 0; i < 3; ++i) {
unsigned a = 0, b = 0;
for (int j = (32 < bitsRemaining ? 31 : bitsRemaining-1); j >=0; --j) {
switch (val[idx]) {;
case '0': break;
case '1': a |= (0x1 << j); break;
case 'X': case 'x': a |= (0x1 << j); break;
case 'Z': case 'z': a |= (0x1 << j); b |= (0x1 << j); break;
default: assert(0); break;
}
idx++;
}
bitsRemaining -= 32;
lv.set_word(3-1-i, (unsigned long) a);
lv.set_cword(3-1-i, (unsigned long) b);
}
return lv;
}
sc_signal > R13_op1;
sc_signal > R13_op2;
sc_signal > R13_op3;
sc_signal R13_iv, R13_ov;

class I13_c : public sc_foreign_module {
public:
sc_in > op1;
sc_in > op2;
sc_out > op3;
sc_in iv;
sc_out ov;
I13_c(sc_module_name nm) :
sc_foreign_module(nm, "I13_c"), op1("op1"), op2("op2"), op3("op3"), iv("iv"), ov("ov") {}
 ~I13_c() {}
};

sc_signal > R14_op1;
sc_signal > R14_op2;
sc_signal R14_iv, R14_ov;

class I14_c : public sc_foreign_module {
public:
sc_in > op1;
sc_out > op2;
sc_in iv;
sc_out ov;
I14_c(sc_module_name nm) :
sc_foreign_module(nm, "I14_c"), op1("op1"), op2("op2"), iv("iv"), ov("ov") {}
 ~I14_c() {}
};

sc_signal > R15_op1;
sc_signal > R15_op2;
sc_signal > R15_op3;
sc_signal R15_iv, R15_ov;

class I15_c : public sc_foreign_module {
public:
sc_in > op1;
sc_in > op2;
sc_out > op3;
sc_in iv;
sc_out ov;
I15_c(sc_module_name nm) :
sc_foreign_module(nm, "I15_c"), op1("op1"), op2("op2"), op3("op3"), iv("iv"), ov("ov") {}
 ~I15_c() {}
};

sc_signal > R16_op1;
sc_signal > R16_op2;
sc_signal R16_iv, R16_ov;

class I16_c : public sc_foreign_module {
public:
sc_in > op1;
sc_out > op2;
sc_in iv;
sc_out ov;
I16_c(sc_module_name nm) :
sc_foreign_module(nm, "I16_c"), op1("op1"), op2("op2"), iv("iv"), ov("ov") {}
 ~I16_c() {}
};

sc_signal > R17_op1;
sc_signal > R17_op2;
sc_signal R17_iv, R17_ov;

class I17_c : public sc_foreign_module {
public:
sc_in > op1;
sc_out > op2;
sc_in iv;
sc_out ov;
I17_c(sc_module_name nm) :
sc_foreign_module(nm, "I17_c"), op1("op1"), op2("op2"), iv("iv"), ov("ov") {}
 ~I17_c() {}
};

sc_signal > R18_op1;
sc_signal > R18_op2;
sc_signal R18_iv, R18_ov;

class I18_c : public sc_foreign_module {
public:
sc_in > op1;
sc_out > op2;
sc_in iv;
sc_out ov;
I18_c(sc_module_name nm) :
sc_foreign_module(nm, "I18_c"), op1("op1"), op2("op2"), iv("iv"), ov("ov") {}
 ~I18_c() {}
};

sc_signal > R19_op1;
sc_signal > R19_op2;
sc_signal R19_iv, R19_ov;

class I19_c : public sc_foreign_module {
public:
sc_in > op1;
sc_out > op2;
sc_in iv;
sc_out ov;
I19_c(sc_module_name nm) :
sc_foreign_module(nm, "I19_c"), op1("op1"), op2("op2"), iv("iv"), ov("ov") {}
 ~I19_c() {}
};

sc_signal > R20_op1;
sc_signal > R20_op2;
sc_signal R20_iv, R20_ov;

class I20_c : public sc_foreign_module {
public:
sc_in > op1;
sc_out > op2;
sc_in iv;
sc_out ov;
I20_c(sc_module_name nm) :
sc_foreign_module(nm, "I20_c"), op1("op1"), op2("op2"), iv("iv"), ov("ov") {}
 ~I20_c() {}
};

sc_signal > R21_op1;
sc_signal > R21_op2;
sc_signal > R21_op3;
sc_signal R21_iv, R21_ov;

class I21_c : public sc_foreign_module {
public:
sc_in > op1;
sc_in > op2;
sc_out > op3;
sc_in iv;
sc_out ov;
I21_c(sc_module_name nm) :
sc_foreign_module(nm, "I21_c"), op1("op1"), op2("op2"), op3("op3"), iv("iv"), ov("ov") {}
 ~I21_c() {}
};

sc_signal > R22_op1;
sc_signal > R22_op2;
sc_signal > R22_op3;
sc_signal R22_iv, R22_ov;

class I22_c : public sc_foreign_module {
public:
sc_in > op1;
sc_in > op2;
sc_out > op3;
sc_in iv;
sc_out ov;
I22_c(sc_module_name nm) :
sc_foreign_module(nm, "I22_c"), op1("op1"), op2("op2"), op3("op3"), iv("iv"), ov("ov") {}
 ~I22_c() {}
};

sc_signal > R23_op1;
sc_signal > R23_op2;
sc_signal > R23_op3;
sc_signal R23_iv, R23_ov;

class I23_c : public sc_foreign_module {
public:
sc_in > op1;
sc_in > op2;
sc_out > op3;
sc_in iv;
sc_out ov;
I23_c(sc_module_name nm) :
sc_foreign_module(nm, "I23_c"), op1("op1"), op2("op2"), op3("op3"), iv("iv"), ov("ov") {}
 ~I23_c() {}
};

sc_signal > R24_op1;
sc_signal > R24_op2;
sc_signal R24_iv, R24_ov;

class I24_c : public sc_foreign_module {
public:
sc_in > op1;
sc_out > op2;
sc_in iv;
sc_out ov;
I24_c(sc_module_name nm) :
sc_foreign_module(nm, "I24_c"), op1("op1"), op2("op2"), iv("iv"), ov("ov") {}
 ~I24_c() {}
};

sc_signal > R25_op1;
sc_signal > R25_op2;
sc_signal > R25_op3;
sc_signal R25_iv, R25_ov;

class I25_c : public sc_foreign_module {
public:
sc_in > op1;
sc_in > op2;
sc_out > op3;
sc_in iv;
sc_out ov;
I25_c(sc_module_name nm) :
sc_foreign_module(nm, "I25_c"), op1("op1"), op2("op2"), op3("op3"), iv("iv"), ov("ov") {}
 ~I25_c() {}
};

sc_signal > R26_op1;
sc_signal > R26_op2;
sc_signal > R26_op3;
sc_signal R26_iv, R26_ov;

class I26_c : public sc_foreign_module {
public:
sc_in > op1;
sc_in > op2;
sc_out > op3;
sc_in iv;
sc_out ov;
I26_c(sc_module_name nm) :
sc_foreign_module(nm, "I26_c"), op1("op1"), op2("op2"), op3("op3"), iv("iv"), ov("ov") {}
 ~I26_c() {}
};

sc_signal > R27_op1;
sc_signal > R27_op2;
sc_signal R27_iv, R27_ov;

class I27_c : public sc_foreign_module {
public:
sc_in > op1;
sc_out > op2;
sc_in iv;
sc_out ov;
I27_c(sc_module_name nm) :
sc_foreign_module(nm, "I27_c"), op1("op1"), op2("op2"), iv("iv"), ov("ov") {}
 ~I27_c() {}
};

sc_signal > R28_op1;
sc_signal > R28_op2;
sc_signal R28_iv, R28_ov;

class I28_c : public sc_foreign_module {
public:
sc_in > op1;
sc_out > op2;
sc_in iv;
sc_out ov;
I28_c(sc_module_name nm) :
sc_foreign_module(nm, "I28_c"), op1("op1"), op2("op2"), iv("iv"), ov("ov") {}
 ~I28_c() {}
};

sc_signal > R29_op1;
sc_signal > R29_op2;
sc_signal R29_iv, R29_ov;

class I29_c : public sc_foreign_module {
public:
sc_in > op1;
sc_out > op2;
sc_in iv;
sc_out ov;
I29_c(sc_module_name nm) :
sc_foreign_module(nm, "I29_c"), op1("op1"), op2("op2"), iv("iv"), ov("ov") {}
 ~I29_c() {}
};

sc_signal > R30_op1;
sc_signal > R30_op2;
sc_signal R30_iv, R30_ov;

class I30_c : public sc_foreign_module {
public:
sc_in > op1;
sc_out > op2;
sc_in iv;
sc_out ov;
I30_c(sc_module_name nm) :
sc_foreign_module(nm, "I30_c"), op1("op1"), op2("op2"), iv("iv"), ov("ov") {}
 ~I30_c() {}
};

sc_signal > R31_address1;
sc_signal > R31_address2;
sc_signal R31_iv, R31_ov;

class I31_c : public sc_foreign_module {
public:
sc_out > address1;
sc_out > address2;
sc_in iv;
sc_out ov;
I31_c(sc_module_name nm) :
sc_foreign_module(nm, "I31_c"), address1("address1"), address2("address2"), iv("iv"), ov("ov") {}
 ~I31_c() {}
};

#ifdef SIM
void copySyscArrayToVer_64_fcomplex_2(const sc_lv<64> *address, int startSc, int startVer, int numWords, double *scArr)
{
simSignalPT signalP;
unsigned long long addr = (((unsigned long long) address->m_ctrl[0]) << 32 | address->m_data[0]);
memcpy(&signalP, &addr, sizeof(unsigned long long));
  finWriteReal1(scArr, signalP, startSc, startVer, numWords, 2);
}
#endif
sc_signal > R32_op1;
sc_signal > R32_op2;
sc_signal > R32_op3;
sc_signal > R32_op4;
sc_signal > R32_op5;
sc_signal > R32_op6;
sc_signal > R32_op7;
sc_signal > R32_op8;
sc_signal > R32_address9;
sc_signal > R32_op10;
sc_signal R32_iv, R32_ov;

class I32_c : public sc_foreign_module {
public:
sc_in > op1;
sc_in > op2;
sc_in > op3;
sc_in > op4;
sc_in > op5;
sc_in > op6;
sc_in > op7;
sc_in > op8;
sc_out > address9;
sc_in > op10;
sc_in iv;
sc_out ov;
I32_c(sc_module_name nm) :
sc_foreign_module(nm, "I32_c"), op1("op1"), op2("op2"), op3("op3"), op4("op4"), op5("op5"), op6("op6"), op7("op7"), op8("op8"), address9("address9"), op10("op10"), iv("iv"), ov("ov") {}
 ~I32_c() {}
};

sc_lv<176> vpNumberToBits_176(const char *val)
{
sc_lv<176> lv;
int bitsRemaining = 176, idx = 0;
for (int i = 0; i < 6; ++i) {
unsigned a = 0, b = 0;
for (int j = (32 < bitsRemaining ? 31 : bitsRemaining-1); j >=0; --j) {
switch (val[idx]) {;
case '0': break;
case '1': a |= (0x1 << j); break;
case 'X': case 'x': a |= (0x1 << j); break;
case 'Z': case 'z': a |= (0x1 << j); b |= (0x1 << j); break;
default: assert(0); break;
}
idx++;
}
bitsRemaining -= 32;
lv.set_word(6-1-i, (unsigned long) a);
lv.set_cword(6-1-i, (unsigned long) b);
}
return lv;
}
#include "/home/alec/finsim/test_rel/10_08_100s/include/sysc/datatypes/fx/scfx_ieee.h"
#include 
class  top_sc : public sc_module {
public:
#include 
SC_CTOR( top_sc) {
SC_THREAD(thread1)
sensitive << od1
 << R1_ov
;

SC_THREAD(thread2)
sensitive << od2
 << R2_ov
 << R3_ov
 << R4_ov
 << R5_ov
 << R6_ov
 << R8_ov
 << R9_ov
 << R11_ov
 << R12_ov
 << R13_ov
 << R14_ov
 << R15_ov
 << R16_ov
 << R17_ov
 << R18_ov
 << R19_ov
 << R20_ov
 << R21_ov
 << R22_ov
 << R23_ov
 << R24_ov
 << R25_ov
 << R26_ov
 << R27_ov
 << R28_ov
 << R29_ov
 << R30_ov
 << R31_ov
 << R32_ov
;

vvpDelta1 *vvpDelta_1;
vvpDelta_1 = new vvpDelta1("vvpDelta_1");
(*vvpDelta_1)(id1, od1);
I1_c *I1;
I1 = new I1_c("I1");
(*I1)(R1_op1, R1_op2, R1_iv, R1_ov);
vvpDelta2 *vvpDelta_2;
vvpDelta_2 = new vvpDelta2("vvpDelta_2");
(*vvpDelta_2)(id2, od2);
Pi_2_c *Pi_2;
Pi_2 = new Pi_2_c("Pi_2");
(*Pi_2)(R2_op2, R2_iv, R2_ov);
I3_c *I3;
I3 = new I3_c("I3");
(*I3)(R3_op1, R3_op2, R3_iv, R3_ov);
I4_c *I4;
I4 = new I4_c("I4");
(*I4)(R4_op1, R4_op2, R4_iv, R4_ov);
I5_c *I5;
I5 = new I5_c("I5");
(*I5)(R5_address1, R5_address2, R5_iv, R5_ov);
VpFft_fcomplex_2_2048_scalar_integer_0_1_scalar_integer_0_1_6_c *VpFft_fcomplex_2_2048_scalar_integer_0_1_scalar_integer_0_1_6;
VpFft_fcomplex_2_2048_scalar_integer_0_1_scalar_integer_0_1_6 = new VpFft_fcomplex_2_2048_scalar_integer_0_1_scalar_integer_0_1_6_c("VpFft_fcomplex_2_2048_scalar_integer_0_1_scalar_integer_0_1_6");
(*VpFft_fcomplex_2_2048_scalar_integer_0_1_scalar_integer_0_1_6)(R6_address1, R6_op2, R6_op3, R6_iv, R6_ov);
I8_c *I8;
I8 = new I8_c("I8");
(*I8)(R8_address1, R8_iv, R8_ov);
I9_c *I9;
I9 = new I9_c("I9");
(*I9)(R9_address1, R9_address2, R9_iv, R9_ov);
I11_c *I11;
I11 = new I11_c("I11");
(*I11)(R11_address1, R11_iv, R11_ov);
I12_c *I12;
I12 = new I12_c("I12");
(*I12)(R12_op1, R12_op2, R12_op3, R12_op4, R12_op5, R12_op6, R12_op7, R12_op8, R12_address9, R12_op10, R12_iv, R12_ov);
I13_c *I13;
I13 = new I13_c("I13");
(*I13)(R13_op1, R13_op2, R13_op3, R13_iv, R13_ov);
I14_c *I14;
I14 = new I14_c("I14");
(*I14)(R14_op1, R14_op2, R14_iv, R14_ov);
I15_c *I15;
I15 = new I15_c("I15");
(*I15)(R15_op1, R15_op2, R15_op3, R15_iv, R15_ov);
I16_c *I16;
I16 = new I16_c("I16");
(*I16)(R16_op1, R16_op2, R16_iv, R16_ov);
I17_c *I17;
I17 = new I17_c("I17");
(*I17)(R17_op1, R17_op2, R17_iv, R17_ov);
I18_c *I18;
I18 = new I18_c("I18");
(*I18)(R18_op1, R18_op2, R18_iv, R18_ov);
I19_c *I19;
I19 = new I19_c("I19");
(*I19)(R19_op1, R19_op2, R19_iv, R19_ov);
I20_c *I20;
I20 = new I20_c("I20");
(*I20)(R20_op1, R20_op2, R20_iv, R20_ov);
I21_c *I21;
I21 = new I21_c("I21");
(*I21)(R21_op1, R21_op2, R21_op3, R21_iv, R21_ov);
I22_c *I22;
I22 = new I22_c("I22");
(*I22)(R22_op1, R22_op2, R22_op3, R22_iv, R22_ov);
I23_c *I23;
I23 = new I23_c("I23");
(*I23)(R23_op1, R23_op2, R23_op3, R23_iv, R23_ov);
I24_c *I24;
I24 = new I24_c("I24");
(*I24)(R24_op1, R24_op2, R24_iv, R24_ov);
I25_c *I25;
I25 = new I25_c("I25");
(*I25)(R25_op1, R25_op2, R25_op3, R25_iv, R25_ov);
I26_c *I26;
I26 = new I26_c("I26");
(*I26)(R26_op1, R26_op2, R26_op3, R26_iv, R26_ov);
I27_c *I27;
I27 = new I27_c("I27");
(*I27)(R27_op1, R27_op2, R27_iv, R27_ov);
I28_c *I28;
I28 = new I28_c("I28");
(*I28)(R28_op1, R28_op2, R28_iv, R28_ov);
I29_c *I29;
I29 = new I29_c("I29");
(*I29)(R29_op1, R29_op2, R29_iv, R29_ov);
I30_c *I30;
I30 = new I30_c("I30");
(*I30)(R30_op1, R30_op2, R30_iv, R30_ov);
I31_c *I31;
I31 = new I31_c("I31");
(*I31)(R31_address1, R31_address2, R31_iv, R31_ov);
I32_c *I32;
I32 = new I32_c("I32");
(*I32)(R32_op1, R32_op2, R32_op3, R32_op4, R32_op5, R32_op6, R32_op7, R32_op8, R32_address9, R32_op10, R32_iv, R32_ov);
} };

#include "fin_sysc_tf.h"
void top_sc::thread1() {
#ifdef SIM
  waitDelta1(id1);
 #endif

   {
#ifdef SIM
R1_op1 = finScRealToBits(5.77215664901532860606512090082402431042e-1);
waitDelta1(id1);
R1_iv = (R1_iv == sc_logic_X || R1_iv == sc_logic_Z) ? sc_logic_1 : ~(R1_iv.read());
wait();
Fin__EM = R1_op2;
#else
vpAssign_scalar_real_0_1_scalar_vp_FLOATING_12_84_0_1(5.77215664901532860606512090082402431042e-1, Fin__EM);
#endif
Fin__I [0] = 0.0;
Fin__I [1] = 1.0;
inf = 0.0;
}
}

#include "fin_sysc_tf.h"
void top_sc::thread2() {
#ifdef SIM
  waitDelta2(id2);
 #endif

   {
#ifdef SIM
waitDelta2(id2);
R2_iv = (R2_iv == sc_logic_X || R2_iv == sc_logic_Z) ? sc_logic_1 : ~(R2_iv.read());
wait();
delta = finScBitsToReal(R2_op2);
#else
delta = Pi();

#endif
delta = ((sc_int<32>)2 * delta);
delta = (delta /(sc_int<32>)1024);
{
   j = 0;
fin_tmp_for_cond_0 =  (sc_logic) (j <(sc_int<32>)1024);
   while (finLogicToBool(fin_tmp_for_cond_0)) 
      {
         tmpr = (delta * j);
         tmpr = (51.20000 * tmpr);
#ifdef SIM
R3_op1 = 0 << 0 ;
waitDelta2(id2);
R3_iv = (R3_iv == sc_logic_X || R3_iv == sc_logic_Z) ? sc_logic_1 : ~(R3_iv.read());
wait();
MyIm [j] = R3_op2;
#else
vpAssign_scalar_integer_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024((sc_int<32>)0, MyIm [j]);
#endif
#ifdef SIM
R4_op1 = finScRealToBits(tmpr);
waitDelta2(id2);
R4_iv = (R4_iv == sc_logic_X || R4_iv == sc_logic_Z) ? sc_logic_1 : ~(R4_iv.read());
wait();
MyRe [j] = R4_op2;
#else
VpSin_scalar_real_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024(tmpr, MyRe [j]);
#endif
j = (j +(sc_int<32>)1);
fin_tmp_for_cond_0 =  (sc_logic) (j <(sc_int<32>)1024);
}
}
copySyscArrayToVer_24_scalar_vp_1024(&(R5_address2.read()), 0, 0, 1024, MyRe);
waitDelta2(id2);
R5_iv = (R5_iv == sc_logic_X || R5_iv == sc_logic_Z) ? sc_logic_1 : ~(R5_iv.read());
wait();
waitDelta2(id2);
copyVerArrayToSysc_64_real(&(R5_address1.read()), 0, 0, 2048, inSpectrum);
#ifdef SIM
copySyscArrayToVer_64_fcomplex_2048(&(R6_address1.read()), 0, 0, 2048, inSpectrum);
R6_op2 = 0 << 0 ;
R6_op3 = 1023 << 0 ;
waitDelta2(id2);
R6_iv = (R6_iv == sc_logic_X || R6_iv == sc_logic_Z) ? sc_logic_1 : ~(R6_iv.read());
wait();
waitDelta2(id2);
copyVerArrayToSysc_64_real(&(R6_address1.read()), 0, 0, 2048, inSpectrum);
#else
VpFft_fcomplex_2_2048_scalar_integer_0_1_scalar_integer_0_1(inSpectrum, 0, 1023);
#endif
copySyscArrayToVer_64_fcomplex_2048(&(R8_address1.read()), 0, 0, 2048, inSpectrum);
waitDelta2(id2);
R8_iv = (R8_iv == sc_logic_X || R8_iv == sc_logic_Z) ? sc_logic_1 : ~(R8_iv.read());
wait();
waitDelta2(id2);
{
   j = 0;
fin_tmp_for_cond_1 =  (sc_logic) (j <(sc_int<32>)512);
   while (finLogicToBool(fin_tmp_for_cond_1)) 
      {
#ifdef SIM
copySyscArrayToVer_64_fcomplex_2048(&(R9_address1.read()), 2*0, 0, 2, inSpectrum);
waitDelta2(id2);
R9_iv = (R9_iv == sc_logic_X || R9_iv == sc_logic_Z) ? sc_logic_1 : ~(R9_iv.read());
wait();
waitDelta2(id2);
copyVerArrayToSysc_64_real(&(R9_address2.read()), 0, 0, 2, polar);
#else
vpAssign_fcomplex_1_2048_2_fpolar_1_2(inSpectrum [j], polar);
#endif
fin__tmp_logical0 =  (sc_logic) (j >=(sc_int<32>)0);
fin__tmp_logical1 =  (sc_logic) (j <=(sc_int<32>)1023);
fin__tmp_logical2 =  (sc_logic) (fin__tmp_logical0& fin__tmp_logical1);
fin__tmp_logical3 =  (sc_logic) (1& fin__tmp_logical2);
fin__tmp_int0 = (j -(sc_int<32>)1023);
fin__tmp_int1 = (j -(sc_int<32>)0);
fin__tmp_simplify_all0 = (( 0 == H)  ?  ((sc_int<32>)  fin__tmp_int0 ) : ((sc_int<32>)  fin__tmp_int1 ));
fin__tmp_simplify_all1 = (fin__tmp_simplify_all0 +(sc_int<32>)0);
fin__tmp_idx0 = (( fin__tmp_logical3 == H)  ?  ((sc_int<32>)  fin__tmp_simplify_all1 ) : ((sc_int<32>) (sc_int<32>)3072 ));
y [fin__tmp_idx0] = polar [0];
j = (j +(sc_int<32>)1);
fin_tmp_for_cond_1 =  (sc_logic) (j <(sc_int<32>)512);
}
}
copySyscArrayToVer_64_scalar_real_3072(&(R11_address1.read()), 0, 0, 3072, y);
waitDelta2(id2);
R11_iv = (R11_iv == sc_logic_X || R11_iv == sc_logic_Z) ? sc_logic_1 : ~(R11_iv.read());
wait();
waitDelta2(id2);
step = 0.39062500000000000000;
#ifdef SIM
R12_op1 = vpNumberToBits_192("010100110111000001100101011000110111010001110010011101010110110101011111010010000110100101100111011010000101111101101100011001010111011001100101011011000010111001101000011101000110110101101100");
R12_op2 = 1 << 0 ;
R12_op3 = finScRealToBits(step);
R12_op4 = vpNumberToBits_64("0101001101110000011001010110001101110100011100100111010101101101");
R12_op5 = vpNumberToBits_120("011001100111001001100101011100010111010101100101011011100110001101111001001000000010100001000111010010000111101000101001");
R12_op6 = vpNumberToBits_80("01000001011011010111000001101100011010010111010001110101011001000110010100100000");
R12_op7 = 0 << 0 ;
R12_op8 = 511 << 0 ;
copySyscArrayToVer_64_scalar_real_3072(&(R12_address9.read()), 0, 0, 3072, y);
R12_op10 = vpNumberToBits_80("01101001011011100101001101110000011001010110001101110100011100100111010101101101");
waitDelta2(id2);
R12_iv = (R12_iv == sc_logic_X || R12_iv == sc_logic_Z) ? sc_logic_1 : ~(R12_iv.read());
wait();
#else
Flot_Spectrum_High_level_html_scalar_integer_0_1_scalar_real_0_1_Spectrum_frequency__GHz__Amplitude__scalar_integer_0_1_scalar_integer_0_1_scalar_real_2_3072_inSpectrum("Spectrum_High_level.html", 1, step, "Spectrum", "frequency (GHz)", "Amplitude ", 0, 511, y, "inSpectrum", );
#endif
sz = 1024;
#ifdef SIM
R13_op1 = finScRealToBits(2.0);
R13_op2 = finScRealToBits(sz);
waitDelta2(id2);
R13_iv = (R13_iv == sc_logic_X || R13_iv == sc_logic_Z) ? sc_logic_1 : ~(R13_iv.read());
wait();
rlogsz = finScBitsToReal(R13_op3);
#else
VpLog_scalar_real_0_1_scalar_real_0_1_scalar_real_0_1(2.0, sz, rlogsz);
#endif
logSize = rlogsz;
n = 1024;
le = (n /(sc_int<32>)2);
#ifdef SIM
R14_op1 = finScRealToBits(1.0);
waitDelta2(id2);
R14_iv = (R14_iv == sc_logic_X || R14_iv == sc_logic_Z) ? sc_logic_1 : ~(R14_iv.read());
wait();
fin__tmp_sysf0 = finScBitsToReal(R14_op2);
#else
VpAtan_scalar_real_0_1_scalar_real_0_1(1.0, fin__tmp_sysf0);
#endif
fin__tmp_real0 = (4.0 * fin__tmp_sysf0);
#ifdef SIM
R15_op1 = finScRealToBits(fin__tmp_real0);
R15_op2 = le;
waitDelta2(id2);
R15_iv = (R15_iv == sc_logic_X || R15_iv == sc_logic_Z) ? sc_logic_1 : ~(R15_iv.read());
wait();
arg = R15_op3;
#else
vpDiv_scalar_real_0_1_integer_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(fin__tmp_real0, le, arg);
#endif
#ifdef SIM
R16_op1 = arg;
waitDelta2(id2);
R16_iv = (R16_iv == sc_logic_X || R16_iv == sc_logic_Z) ? sc_logic_1 : ~(R16_iv.read());
wait();
wrecRe = R16_op2;
#else
VpCos_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(arg, wrecRe);
#endif
#ifdef SIM
R17_op1 = wrecRe;
waitDelta2(id2);
R17_iv = (R17_iv == sc_logic_X || R17_iv == sc_logic_Z) ? sc_logic_1 : ~(R17_iv.read());
wait();
wRe = R17_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(wrecRe, wRe);
#endif
#ifdef SIM
R18_op1 = arg;
waitDelta2(id2);
R18_iv = (R18_iv == sc_logic_X || R18_iv == sc_logic_Z) ? sc_logic_1 : ~(R18_iv.read());
wait();
fin__tmp_sysf1 = finScBitsToReal(R18_op2);
#else
VpSin_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_real_0_1(arg, fin__tmp_sysf1);
#endif
#ifdef SIM
R19_op1 = finScRealToBits((-fin__tmp_sysf1));
waitDelta2(id2);
R19_iv = (R19_iv == sc_logic_X || R19_iv == sc_logic_Z) ? sc_logic_1 : ~(R19_iv.read());
wait();
wrecIm = R19_op2;
#else
vpAssign_scalar_real_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1((-fin__tmp_sysf1), wrecIm);
#endif
#ifdef SIM
R17_op1 = wrecIm;
waitDelta2(id2);
R17_iv = (R17_iv == sc_logic_X || R17_iv == sc_logic_Z) ? sc_logic_1 : ~(R17_iv.read());
wait();
wIm = R17_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(wrecIm, wIm);
#endif
{
   j = 0;
fin__tmp_int2 = (le -(sc_int<32>)1);
   fin__tmp_logical4 =  (sc_logic) (j < fin__tmp_int2);
   fin_tmp_for_cond_2 = fin__tmp_logical4;
while (finLogicToBool(fin_tmp_for_cond_2)) 
      {
#ifdef SIM
R20_op1 = wrecRe;
waitDelta2(id2);
R20_iv = (R20_iv == sc_logic_X || R20_iv == sc_logic_Z) ? sc_logic_1 : ~(R20_iv.read());
wait();
MywReV [j] = R20_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_512(wrecRe, MywReV [j]);
#endif
#ifdef SIM
R20_op1 = wrecIm;
waitDelta2(id2);
R20_iv = (R20_iv == sc_logic_X || R20_iv == sc_logic_Z) ? sc_logic_1 : ~(R20_iv.read());
wait();
MywImV [j] = R20_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_512(wrecIm, MywImV [j]);
#endif
#ifdef SIM
R21_op1 = wrecRe;
R21_op2 = wRe;
waitDelta2(id2);
R21_iv = (R21_iv == sc_logic_X || R21_iv == sc_logic_Z) ? sc_logic_1 : ~(R21_iv.read());
wait();
tmpvp1 = R21_op3;
#else
vpMult_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(wrecRe, wRe, tmpvp1);
#endif
#ifdef SIM
R21_op1 = wrecIm;
R21_op2 = wIm;
waitDelta2(id2);
R21_iv = (R21_iv == sc_logic_X || R21_iv == sc_logic_Z) ? sc_logic_1 : ~(R21_iv.read());
wait();
tmpvp2 = R21_op3;
#else
vpMult_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(wrecIm, wIm, tmpvp2);
#endif
#ifdef SIM
R22_op1 = tmpvp1;
R22_op2 = tmpvp2;
waitDelta2(id2);
R22_iv = (R22_iv == sc_logic_X || R22_iv == sc_logic_Z) ? sc_logic_1 : ~(R22_iv.read());
wait();
wtemp = R22_op3;
#else
vpSub_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(tmpvp1, tmpvp2, wtemp);
#endif
#ifdef SIM
R21_op1 = wrecRe;
R21_op2 = wIm;
waitDelta2(id2);
R21_iv = (R21_iv == sc_logic_X || R21_iv == sc_logic_Z) ? sc_logic_1 : ~(R21_iv.read());
wait();
tmpvp1 = R21_op3;
#else
vpMult_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(wrecRe, wIm, tmpvp1);
#endif
#ifdef SIM
R21_op1 = wrecIm;
R21_op2 = wRe;
waitDelta2(id2);
R21_iv = (R21_iv == sc_logic_X || R21_iv == sc_logic_Z) ? sc_logic_1 : ~(R21_iv.read());
wait();
tmpvp2 = R21_op3;
#else
vpMult_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(wrecIm, wRe, tmpvp2);
#endif
#ifdef SIM
R23_op1 = tmpvp1;
R23_op2 = tmpvp2;
waitDelta2(id2);
R23_iv = (R23_iv == sc_logic_X || R23_iv == sc_logic_Z) ? sc_logic_1 : ~(R23_iv.read());
wait();
wrecIm = R23_op3;
#else
vpAdd_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(tmpvp1, tmpvp2, wrecIm);
#endif
#ifdef SIM
R17_op1 = wtemp;
waitDelta2(id2);
R17_iv = (R17_iv == sc_logic_X || R17_iv == sc_logic_Z) ? sc_logic_1 : ~(R17_iv.read());
wait();
wrecRe = R17_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(wtemp, wrecRe);
#endif
j = (j +(sc_int<32>)1);
fin__tmp_int3 = (le -(sc_int<32>)1);
fin__tmp_logical5 =  (sc_logic) (j < fin__tmp_int3);
fin_tmp_for_cond_2 = fin__tmp_logical5;
}
}
le = n;
windex = 1;
{
l = 0;
fin_tmp_for_cond_3 =  (sc_logic) (l < logSize);
while (finLogicToBool(fin_tmp_for_cond_3)) 
{
le = (le /(sc_int<32>)2);
{
   i = 0;
fin_tmp_for_cond_4 =  (sc_logic) (i < n);
   while (finLogicToBool(fin_tmp_for_cond_4)) 
      {
#ifdef SIM
R24_op1 = MyRe [i];
waitDelta2(id2);
R24_iv = (R24_iv == sc_logic_X || R24_iv == sc_logic_Z) ? sc_logic_1 : ~(R24_iv.read());
wait();
tmp1Re = R24_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(MyRe [i], tmp1Re);
#endif
#ifdef SIM
R24_op1 = MyIm [i];
waitDelta2(id2);
R24_iv = (R24_iv == sc_logic_X || R24_iv == sc_logic_Z) ? sc_logic_1 : ~(R24_iv.read());
wait();
tmp1Im = R24_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(MyIm [i], tmp1Im);
#endif
fin__tmp_idx1 = (i + le);
#ifdef SIM
R24_op1 = MyRe [fin__tmp_idx1];
waitDelta2(id2);
R24_iv = (R24_iv == sc_logic_X || R24_iv == sc_logic_Z) ? sc_logic_1 : ~(R24_iv.read());
wait();
tmp2Re = R24_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(MyRe [fin__tmp_idx1], tmp2Re);
#endif
fin__tmp_idx2 = (i + le);
#ifdef SIM
R24_op1 = MyIm [fin__tmp_idx2];
waitDelta2(id2);
R24_iv = (R24_iv == sc_logic_X || R24_iv == sc_logic_Z) ? sc_logic_1 : ~(R24_iv.read());
wait();
tmp2Im = R24_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(MyIm [fin__tmp_idx2], tmp2Im);
#endif
#ifdef SIM
R25_op1 = tmp1Re;
R25_op2 = tmp2Re;
waitDelta2(id2);
R25_iv = (R25_iv == sc_logic_X || R25_iv == sc_logic_Z) ? sc_logic_1 : ~(R25_iv.read());
wait();
MyRe [i] = R25_op3;
#else
vpAdd_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024(tmp1Re, tmp2Re, MyRe [i]);
#endif
#ifdef SIM
R25_op1 = tmp1Im;
R25_op2 = tmp2Im;
waitDelta2(id2);
R25_iv = (R25_iv == sc_logic_X || R25_iv == sc_logic_Z) ? sc_logic_1 : ~(R25_iv.read());
wait();
MyIm [i] = R25_op3;
#else
vpAdd_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024(tmp1Im, tmp2Im, MyIm [i]);
#endif
fin__tmp_idx3 = (i + le);
#ifdef SIM
R26_op1 = tmp1Re;
R26_op2 = tmp2Re;
waitDelta2(id2);
R26_iv = (R26_iv == sc_logic_X || R26_iv == sc_logic_Z) ? sc_logic_1 : ~(R26_iv.read());
wait();
MyRe [fin__tmp_idx3] = R26_op3;
#else
vpSub_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024(tmp1Re, tmp2Re, MyRe [fin__tmp_idx3]);
#endif
fin__tmp_idx4 = (i + le);
#ifdef SIM
R26_op1 = tmp1Im;
R26_op2 = tmp2Im;
waitDelta2(id2);
R26_iv = (R26_iv == sc_logic_X || R26_iv == sc_logic_Z) ? sc_logic_1 : ~(R26_iv.read());
wait();
MyIm [fin__tmp_idx4] = R26_op3;
#else
vpSub_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024(tmp1Im, tmp2Im, MyIm [fin__tmp_idx4]);
#endif
fin__tmp_int4 = ((sc_int<32>)2 * le);
i = (i + fin__tmp_int4);
fin_tmp_for_cond_4 =  (sc_logic) (i < n);
}
}
wptr = (windex -(sc_int<32>)1);
{
j = 1;
fin_tmp_for_cond_5 =  (sc_logic) (j < le);
while (finLogicToBool(fin_tmp_for_cond_5)) 
{
#ifdef SIM
R27_op1 = MywReV [wptr];
waitDelta2(id2);
R27_iv = (R27_iv == sc_logic_X || R27_iv == sc_logic_Z) ? sc_logic_1 : ~(R27_iv.read());
wait();
uRe = R27_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_512_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(MywReV [wptr], uRe);
#endif
#ifdef SIM
R27_op1 = MywImV [wptr];
waitDelta2(id2);
R27_iv = (R27_iv == sc_logic_X || R27_iv == sc_logic_Z) ? sc_logic_1 : ~(R27_iv.read());
wait();
uIm = R27_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_512_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(MywImV [wptr], uIm);
#endif
{
   i = j;
fin_tmp_for_cond_6 =  (sc_logic) (i < n);
   while (finLogicToBool(fin_tmp_for_cond_6)) 
      {
         #ifdef SIM
R24_op1 = MyRe [i];
waitDelta2(id2);
R24_iv = (R24_iv == sc_logic_X || R24_iv == sc_logic_Z) ? sc_logic_1 : ~(R24_iv.read());
wait();
tmp1Re = R24_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(MyRe [i], tmp1Re);
#endif
#ifdef SIM
R24_op1 = MyIm [i];
waitDelta2(id2);
R24_iv = (R24_iv == sc_logic_X || R24_iv == sc_logic_Z) ? sc_logic_1 : ~(R24_iv.read());
wait();
tmp1Im = R24_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(MyIm [i], tmp1Im);
#endif
fin__tmp_idx5 = (i + le);
#ifdef SIM
R24_op1 = MyRe [fin__tmp_idx5];
waitDelta2(id2);
R24_iv = (R24_iv == sc_logic_X || R24_iv == sc_logic_Z) ? sc_logic_1 : ~(R24_iv.read());
wait();
tmp2Re = R24_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(MyRe [fin__tmp_idx5], tmp2Re);
#endif
fin__tmp_idx6 = (i + le);
#ifdef SIM
R24_op1 = MyIm [fin__tmp_idx6];
waitDelta2(id2);
R24_iv = (R24_iv == sc_logic_X || R24_iv == sc_logic_Z) ? sc_logic_1 : ~(R24_iv.read());
wait();
tmp2Im = R24_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(MyIm [fin__tmp_idx6], tmp2Im);
#endif
#ifdef SIM
R25_op1 = tmp1Re;
R25_op2 = tmp2Re;
waitDelta2(id2);
R25_iv = (R25_iv == sc_logic_X || R25_iv == sc_logic_Z) ? sc_logic_1 : ~(R25_iv.read());
wait();
MyRe [i] = R25_op3;
#else
vpAdd_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024(tmp1Re, tmp2Re, MyRe [i]);
#endif
#ifdef SIM
R25_op1 = tmp1Im;
R25_op2 = tmp2Im;
waitDelta2(id2);
R25_iv = (R25_iv == sc_logic_X || R25_iv == sc_logic_Z) ? sc_logic_1 : ~(R25_iv.read());
wait();
MyIm [i] = R25_op3;
#else
vpAdd_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024(tmp1Im, tmp2Im, MyIm [i]);
#endif
#ifdef SIM
R22_op1 = tmp1Re;
R22_op2 = tmp2Re;
waitDelta2(id2);
R22_iv = (R22_iv == sc_logic_X || R22_iv == sc_logic_Z) ? sc_logic_1 : ~(R22_iv.read());
wait();
tmRe = R22_op3;
#else
vpSub_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(tmp1Re, tmp2Re, tmRe);
#endif
#ifdef SIM
R22_op1 = tmp1Im;
R22_op2 = tmp2Im;
waitDelta2(id2);
R22_iv = (R22_iv == sc_logic_X || R22_iv == sc_logic_Z) ? sc_logic_1 : ~(R22_iv.read());
wait();
tmIm = R22_op3;
#else
vpSub_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(tmp1Im, tmp2Im, tmIm);
#endif
#ifdef SIM
R21_op1 = tmRe;
R21_op2 = uRe;
waitDelta2(id2);
R21_iv = (R21_iv == sc_logic_X || R21_iv == sc_logic_Z) ? sc_logic_1 : ~(R21_iv.read());
wait();
tmpvp1 = R21_op3;
#else
vpMult_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(tmRe, uRe, tmpvp1);
#endif
#ifdef SIM
R21_op1 = tmIm;
R21_op2 = uIm;
waitDelta2(id2);
R21_iv = (R21_iv == sc_logic_X || R21_iv == sc_logic_Z) ? sc_logic_1 : ~(R21_iv.read());
wait();
tmpvp2 = R21_op3;
#else
vpMult_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(tmIm, uIm, tmpvp2);
#endif
fin__tmp_idx7 = (i + le);
#ifdef SIM
R26_op1 = tmpvp1;
R26_op2 = tmpvp2;
waitDelta2(id2);
R26_iv = (R26_iv == sc_logic_X || R26_iv == sc_logic_Z) ? sc_logic_1 : ~(R26_iv.read());
wait();
MyRe [fin__tmp_idx7] = R26_op3;
#else
vpSub_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024(tmpvp1, tmpvp2, MyRe [fin__tmp_idx7]);
#endif
#ifdef SIM
R21_op1 = tmRe;
R21_op2 = uIm;
waitDelta2(id2);
R21_iv = (R21_iv == sc_logic_X || R21_iv == sc_logic_Z) ? sc_logic_1 : ~(R21_iv.read());
wait();
tmpvp1 = R21_op3;
#else
vpMult_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(tmRe, uIm, tmpvp1);
#endif
#ifdef SIM
R21_op1 = tmIm;
R21_op2 = uRe;
waitDelta2(id2);
R21_iv = (R21_iv == sc_logic_X || R21_iv == sc_logic_Z) ? sc_logic_1 : ~(R21_iv.read());
wait();
tmpvp2 = R21_op3;
#else
vpMult_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(tmIm, uRe, tmpvp2);
#endif
fin__tmp_idx8 = (i + le);
#ifdef SIM
R25_op1 = tmpvp1;
R25_op2 = tmpvp2;
waitDelta2(id2);
R25_iv = (R25_iv == sc_logic_X || R25_iv == sc_logic_Z) ? sc_logic_1 : ~(R25_iv.read());
wait();
MyIm [fin__tmp_idx8] = R25_op3;
#else
vpAdd_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024(tmpvp1, tmpvp2, MyIm [fin__tmp_idx8]);
#endif
fin__tmp_int5 = ((sc_int<32>)2 * le);
i = (i + fin__tmp_int5);
fin_tmp_for_cond_6 =  (sc_logic) (i < n);
}
}
wptr = (wptr + windex);
j = (j +(sc_int<32>)1);
fin_tmp_for_cond_5 =  (sc_logic) (j < le);
}
}
windex = (windex *(sc_int<32>)2);
l = (l +(sc_int<32>)1);
fin_tmp_for_cond_3 =  (sc_logic) (l < logSize);
}
}
j = 0;
{
i = 1;
fin__tmp_int6 = (n -(sc_int<32>)1);
fin__tmp_logical6 =  (sc_logic) (i < fin__tmp_int6);
fin_tmp_for_cond_7 = fin__tmp_logical6;
while (finLogicToBool(fin_tmp_for_cond_7)) 
{
k = (n /(sc_int<32>)2);
{
fin_tmp_cond_while_0 =  (sc_logic) (k <= j);
while (finLogicToBool(fin_tmp_cond_while_0)) 
{
j = (j - k);
k = (k /(sc_int<32>)2);
fin_tmp_cond_while_0 =  (sc_logic) (k <= j);
}
}
j = (j + k);
{
fin_tmp_cond_if_0 =  (sc_logic) (i < j);
if (finLogicToBool(fin_tmp_cond_if_0)) { 
{
#ifdef SIM
R24_op1 = MyRe [j];
waitDelta2(id2);
R24_iv = (R24_iv == sc_logic_X || R24_iv == sc_logic_Z) ? sc_logic_1 : ~(R24_iv.read());
wait();
tempRe = R24_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(MyRe [j], tempRe);
#endif
#ifdef SIM
R24_op1 = MyIm [j];
waitDelta2(id2);
R24_iv = (R24_iv == sc_logic_X || R24_iv == sc_logic_Z) ? sc_logic_1 : ~(R24_iv.read());
wait();
tempIm = R24_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024_scalar_vp_TWOS_COMPLEMENT_9_15_0_1(MyIm [j], tempIm);
#endif
#ifdef SIM
R28_op1 = MyRe [i];
waitDelta2(id2);
R28_iv = (R28_iv == sc_logic_X || R28_iv == sc_logic_Z) ? sc_logic_1 : ~(R28_iv.read());
wait();
MyRe [j] = R28_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024(MyRe [i], MyRe [j]);
#endif
#ifdef SIM
R28_op1 = MyIm [i];
waitDelta2(id2);
R28_iv = (R28_iv == sc_logic_X || R28_iv == sc_logic_Z) ? sc_logic_1 : ~(R28_iv.read());
wait();
MyIm [j] = R28_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024(MyIm [i], MyIm [j]);
#endif
#ifdef SIM
R29_op1 = tempRe;
waitDelta2(id2);
R29_iv = (R29_iv == sc_logic_X || R29_iv == sc_logic_Z) ? sc_logic_1 : ~(R29_iv.read());
wait();
MyRe [i] = R29_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024(tempRe, MyRe [i]);
#endif
#ifdef SIM
R29_op1 = tempIm;
waitDelta2(id2);
R29_iv = (R29_iv == sc_logic_X || R29_iv == sc_logic_Z) ? sc_logic_1 : ~(R29_iv.read());
wait();
MyIm [i] = R29_op2;
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024(tempIm, MyIm [i]);
#endif
}
}}
i = (i +(sc_int<32>)1);
fin__tmp_int7 = (n -(sc_int<32>)1);
fin__tmp_logical7 =  (sc_logic) (i < fin__tmp_int7);
fin_tmp_for_cond_7 = fin__tmp_logical7;
}
}
{
j = 0;
fin_tmp_for_cond_8 =  (sc_logic) (j <(sc_int<32>)512);
while (finLogicToBool(fin_tmp_for_cond_8)) 
{
#ifdef SIM
R30_op1 = MyRe [j];
waitDelta2(id2);
R30_iv = (R30_iv == sc_logic_X || R30_iv == sc_logic_Z) ? sc_logic_1 : ~(R30_iv.read());
wait();
cart [0] = finScBitsToReal(R30_op2);
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024_fcomplex_0_2(MyRe [j], cart [(sc_int<32>)0]);
#endif
#ifdef SIM
R30_op1 = MyIm [j];
waitDelta2(id2);
R30_iv = (R30_iv == sc_logic_X || R30_iv == sc_logic_Z) ? sc_logic_1 : ~(R30_iv.read());
wait();
cart [1] = finScBitsToReal(R30_op2);
#else
vpAssign_scalar_vp_TWOS_COMPLEMENT_9_15_0_1024_fcomplex_0_2(MyIm [j], cart [(sc_int<32>)1]);
#endif
#ifdef SIM
copySyscArrayToVer_64_fcomplex_2(&(R31_address1.read()), 0, 0, 2, cart);
waitDelta2(id2);
R31_iv = (R31_iv == sc_logic_X || R31_iv == sc_logic_Z) ? sc_logic_1 : ~(R31_iv.read());
wait();
waitDelta2(id2);
copyVerArrayToSysc_64_real(&(R31_address2.read()), 0, 0, 2, polar);
#else
vpAssign_fcomplex_1_2_fpolar_1_2(cart, polar);
#endif
fin__tmp_logical8 =  (sc_logic) (j >=(sc_int<32>)0);
fin__tmp_logical9 =  (sc_logic) (j <=(sc_int<32>)1023);
fin__tmp_logical10 =  (sc_logic) (fin__tmp_logical8& fin__tmp_logical9);
fin__tmp_logical11 =  (sc_logic) (1& fin__tmp_logical10);
fin__tmp_int8 = (j -(sc_int<32>)1023);
fin__tmp_int9 = (j -(sc_int<32>)0);
fin__tmp_simplify_all2 = (( 0 == H)  ?  ((sc_int<32>)  fin__tmp_int8 ) : ((sc_int<32>)  fin__tmp_int9 ));
fin__tmp_simplify_all3 = (fin__tmp_simplify_all2 +(sc_int<32>)0);
fin__tmp_idx9 = (( fin__tmp_logical11 == H)  ?  ((sc_int<32>)  fin__tmp_simplify_all3 ) : ((sc_int<32>) (sc_int<32>)3072 ));
y [fin__tmp_idx9] = polar [0];
j = (j +(sc_int<32>)1);
fin_tmp_for_cond_8 =  (sc_logic) (j <(sc_int<32>)512);
}
}
step = 0.39062500000000000000;
#ifdef SIM
R32_op1 = vpNumberToBits_176("01010011011100000110010101100011011101000111001001110101011011010101111101100100011001010111010001100001011010010110110001100101011001000010111001101000011101000110110101101100");
R32_op2 = 1 << 0 ;
R32_op3 = finScRealToBits(step);
R32_op4 = vpNumberToBits_64("0101001101110000011001010110001101110100011100100111010101101101");
R32_op5 = vpNumberToBits_120("011001100111001001100101011100010111010101100101011011100110001101111001001000000010100001000111010010000111101000101001");
R32_op6 = vpNumberToBits_80("01000001011011010111000001101100011010010111010001110101011001000110010100100000");
R32_op7 = 0 << 0 ;
R32_op8 = 511 << 0 ;
copySyscArrayToVer_64_scalar_real_3072(&(R32_address9.read()), 0, 0, 3072, y);
R32_op10 = vpNumberToBits_80("01101001011011100101001101110000011001010110001101110100011100100111010101101101");
waitDelta2(id2);
R32_iv = (R32_iv == sc_logic_X || R32_iv == sc_logic_Z) ? sc_logic_1 : ~(R32_iv.read());
wait();
#else
Flot_Spectrum_detailed_html_scalar_integer_0_1_scalar_real_0_1_Spectrum_frequency__GHz__Amplitude__scalar_integer_0_1_scalar_integer_0_1_scalar_real_2_3072_inSpectrum("Spectrum_detailed.html", 1, step, "Spectrum", "frequency (GHz)", "Amplitude ", 0, 511, y, "inSpectrum", );
#endif
#ifdef SIM
cout << "Simulation Finished";
cout << "\n";
#endif
}
}
The generated file fin_sysc.v is presented below: 
module  top;
 top_sc  top_sc ();
 endmodule
 module top_sc;
 (* foreign = SystemC *)
 endmodule
module vvpDelta1(iv, ov);
input iv;
output ov;
reg ov;
always@(iv)
  begin
    ov = iv;
  end
endmodule

module I1_c(
op1, op2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
output op2;
input iv;
output ov;
wire [0:63] op1;
reg [0:95] op2;
reg ov;
wire iv;
real vpOp1;
VpReg [0:95] vpOp2;
initial begin
  $VpSetDescriptorInfo(Fin__descr, 12, 84, `FLOATING, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp2, Fin__descr);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $bitstoreal(op1);
    vpOp2 =      vpOp1;
;
    op2 = vpOp2;
    ov = ~ov;
  end
end
endmodule

module vvpDelta2(iv, ov);
input iv;
output ov;
reg ov;
always@(iv)
  begin
    ov = iv;
  end
endmodule

module Pi_2_c(
op1, iv, ov);
`include "finsimmath.h"
output op1;
input iv;
output ov;
reg [0:63] op1;
reg ov;
wire iv;
real vpOp1;
initial begin
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $Pi;
op1 = $realtobits(vpOp1);    ov = ~ov;
  end
end
endmodule

module I3_c(
op1, op2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
output op2;
input iv;
output ov;
wire [0:31] op1;
reg [0:23] op2;
reg ov;
wire iv;
VpDescriptor d1;
integer vpOp1;
VpReg [0:23] vpOp2;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp2, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = op1;
    vpOp2 =      vpOp1;
;
    op2 = vpOp2;
    ov = ~ov;
  end
end
endmodule

module I4_c(
op1, op2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
output op2;
input iv;
output ov;
wire [0:63] op1;
reg [0:23] op2;
reg ov;
wire iv;
VpDescriptor d1;
real vpOp1;
VpReg [0:23] vpOp2;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp2, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $bitstoreal(op1);
   vpOp2 = $VpSin(vpOp1
);
    op2 = vpOp2;
    ov = ~ov;
  end
end
endmodule

module I5_c(
address1, address2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
output address1;
output address2;
input iv;
output ov;
reg [0:63] address1;
reg [0:63] address2;
reg ov;
wire iv;
VpDescriptor d1;
VpFCartesian vpOp1 [0:1023];
VpReg [0:23] vpOp2 [0:1023];
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToDataV(vpOp2, d1);
  ov = 1'b0;
  address1 = $VpAddress(vpOp1);
  address2 = $VpAddress(vpOp2);
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
$InitM(vpOp1,vpOp2 [$I1],0);
    ov = ~ov;
  end
end
endmodule

module VpFft_fcomplex_2_2048_scalar_integer_0_1_scalar_integer_0_1_6_c(
address1, op2, op3, iv, ov);
`include "finsimmath.h"
output address1;
input op2;
input op3;
input iv;
output ov;
reg [0:63] address1;
wire [0:31] op2;
wire [0:31] op3;
reg ov;
wire iv;
VpFCartesian vpOp1 [0:1023];
integer vpOp2;
integer vpOp3;
initial begin
  ov = 1'b0;
  address1 = $VpAddress(vpOp1);
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp2 = op2;
    vpOp3 = op3;
$VpFft(vpOp1
, vpOp2
, vpOp3
);
    ov = ~ov;
  end
end
endmodule

module I8_c(
address1, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
output address1;
input iv;
output ov;
reg [0:63] address1;
reg ov;
wire iv;
VpFCartesian inSpectrum [0:1023];
initial begin
  ov = 1'b0;
  address1 = $VpAddress(inSpectrum);
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
$PrintM(inSpectrum
, "%e");
    ov = ~ov;
  end
end
endmodule

module I9_c(
address1, address2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
output address1;
output address2;
input iv;
output ov;
reg [0:63] address1;
reg [0:63] address2;
reg ov;
wire iv;
VpFCartesian vpOp1;
VpFPolar vpOp2;
initial begin
  ov = 1'b0;
  address1 = $VpAddress(vpOp1);
  address2 = $VpAddress(vpOp2);
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp2 =      vpOp1;
;
    ov = ~ov;
  end
end
endmodule

module I11_c(
address1, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
output address1;
input iv;
output ov;
reg [0:63] address1;
reg ov;
wire iv;
real y [0:2][0:1023];
initial begin
  ov = 1'b0;
  address1 = $VpAddress(y);
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
$PrintM(y
, "%e");
    ov = ~ov;
  end
end
endmodule

module I12_c(
op1, op2, op3, op4, op5, op6, op7, op8, address9, op10, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
input op2;
input op3;
input op4;
input op5;
input op6;
input op7;
input op8;
output address9;
input op10;
input iv;
output ov;
wire [0:191] op1;
wire [0:31] op2;
wire [0:63] op3;
wire [0:63] op4;
wire [0:119] op5;
wire [0:79] op6;
wire [0:31] op7;
wire [0:31] op8;
reg [0:63] address9;
wire [0:79] op10;
reg ov;
wire iv;
integer vpOp2;
real vpOp3;
integer vpOp7;
integer vpOp8;
real vpOp9 [0:2][0:1023];
initial begin
  ov = 1'b0;
  address9 = $VpAddress(vpOp9);
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp2 = op2;
    vpOp3 = $bitstoreal(op3);
    vpOp7 = op7;
    vpOp8 = op8;
$Flot("Spectrum_High_level.html", vpOp2
, vpOp3
, "Spectrum", "frequency (GHz)", "Amplitude ", vpOp7
, vpOp8
, vpOp9
, "inSpectrum");
    ov = ~ov;
  end
end
endmodule

module I13_c(
op1, op2, op3, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
input op2;
output op3;
input iv;
output ov;
wire [0:63] op1;
wire [0:63] op2;
reg [0:63] op3;
reg ov;
wire iv;
real vpOp1;
real vpOp2;
real vpOp3;
initial begin
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $bitstoreal(op1);
    vpOp2 = $bitstoreal(op2);
   vpOp3 = $VpLog(vpOp1
, vpOp2
);
    op3 = $realtobits(vpOp3);
    ov = ~ov;
  end
end
endmodule

module I14_c(
op1, op2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
output op2;
input iv;
output ov;
wire [0:63] op1;
reg [0:63] op2;
reg ov;
wire iv;
real vpOp1;
real vpOp2;
initial begin
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $bitstoreal(op1);
   vpOp2 = $VpAtan(vpOp1
);
    op2 = $realtobits(vpOp2);
    ov = ~ov;
  end
end
endmodule

module I15_c(
op1, op2, op3, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
input op2;
output op3;
input iv;
output ov;
wire [0:63] op1;
wire [0:31] op2;
reg [0:23] op3;
reg ov;
wire iv;
VpDescriptor d1;
real vpOp1;
VpReg [0:23] vpOp3;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp3, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $bitstoreal(op1);
    vpOp3 = vpOp1 / op2;
    op3 = vpOp3;
    ov = ~ov;
  end
end
endmodule

module I16_c(
op1, op2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
output op2;
input iv;
output ov;
wire [0:23] op1;
reg [0:23] op2;
reg ov;
wire iv;
VpDescriptor d1;
VpReg [0:23] vpOp1;
VpReg [0:23] vpOp2;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp1, d1);
  $VpAssocDescrToData(vpOp2, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $VpCopyReg2Vp(op1);
   vpOp2 = $VpCos(vpOp1
);
    op2 = vpOp2;
    ov = ~ov;
  end
end
endmodule

module I17_c(
op1, op2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
output op2;
input iv;
output ov;
wire [0:23] op1;
reg [0:23] op2;
reg ov;
wire iv;
VpDescriptor d1;
VpReg [0:23] vpOp1;
VpReg [0:23] vpOp2;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp1, d1);
  $VpAssocDescrToData(vpOp2, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $VpCopyReg2Vp(op1);
    vpOp2 =      vpOp1;
;
    op2 = vpOp2;
    ov = ~ov;
  end
end
endmodule

module I18_c(
op1, op2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
output op2;
input iv;
output ov;
wire [0:23] op1;
reg [0:63] op2;
reg ov;
wire iv;
VpDescriptor d1;
VpReg [0:23] vpOp1;
real vpOp2;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp1, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $VpCopyReg2Vp(op1);
   vpOp2 = $VpSin(vpOp1
);
    op2 = $realtobits(vpOp2);
    ov = ~ov;
  end
end
endmodule

module I19_c(
op1, op2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
output op2;
input iv;
output ov;
wire [0:63] op1;
reg [0:23] op2;
reg ov;
wire iv;
VpDescriptor d1;
real vpOp1;
VpReg [0:23] vpOp2;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp2, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $bitstoreal(op1);
    vpOp2 =      -vpOp1;
;
    op2 = vpOp2;
    ov = ~ov;
  end
end
endmodule

module I20_c(
op1, op2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
output op2;
input iv;
output ov;
wire [0:23] op1;
reg [0:23] op2;
reg ov;
wire iv;
VpDescriptor d1;
VpReg [0:23] vpOp1;
VpReg [0:23] vpOp2;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp1, d1);
  $VpAssocDescrToData(vpOp2, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $VpCopyReg2Vp(op1);
    vpOp2 =      vpOp1;
;
    op2 = vpOp2;
    ov = ~ov;
  end
end
endmodule

module I21_c(
op1, op2, op3, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
input op2;
output op3;
input iv;
output ov;
wire [0:23] op1;
wire [0:23] op2;
reg [0:23] op3;
reg ov;
wire iv;
VpDescriptor d1;
VpReg [0:23] vpOp1;
VpReg [0:23] vpOp2;
VpReg [0:23] vpOp3;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp1, d1);
  $VpAssocDescrToData(vpOp2, d1);
  $VpAssocDescrToData(vpOp3, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $VpCopyReg2Vp(op1);
    vpOp2 = $VpCopyReg2Vp(op2);
    vpOp3 = vpOp1 * vpOp2;
    op3 = vpOp3;
    ov = ~ov;
  end
end
endmodule

module I22_c(
op1, op2, op3, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
input op2;
output op3;
input iv;
output ov;
wire [0:23] op1;
wire [0:23] op2;
reg [0:23] op3;
reg ov;
wire iv;
VpDescriptor d1;
VpReg [0:23] vpOp1;
VpReg [0:23] vpOp2;
VpReg [0:23] vpOp3;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp1, d1);
  $VpAssocDescrToData(vpOp2, d1);
  $VpAssocDescrToData(vpOp3, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $VpCopyReg2Vp(op1);
    vpOp2 = $VpCopyReg2Vp(op2);
    vpOp3 = vpOp1 - vpOp2;
    op3 = vpOp3;
    ov = ~ov;
  end
end
endmodule

module I23_c(
op1, op2, op3, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
input op2;
output op3;
input iv;
output ov;
wire [0:23] op1;
wire [0:23] op2;
reg [0:23] op3;
reg ov;
wire iv;
VpDescriptor d1;
VpReg [0:23] vpOp1;
VpReg [0:23] vpOp2;
VpReg [0:23] vpOp3;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp1, d1);
  $VpAssocDescrToData(vpOp2, d1);
  $VpAssocDescrToData(vpOp3, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $VpCopyReg2Vp(op1);
    vpOp2 = $VpCopyReg2Vp(op2);
    vpOp3 = vpOp1 + vpOp2;
    op3 = vpOp3;
    ov = ~ov;
  end
end
endmodule

module I24_c(
op1, op2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
output op2;
input iv;
output ov;
wire [0:23] op1;
reg [0:23] op2;
reg ov;
wire iv;
VpDescriptor d1;
VpReg [0:23] vpOp1;
VpReg [0:23] vpOp2;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp1, d1);
  $VpAssocDescrToData(vpOp2, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $VpCopyReg2Vp(op1);
    vpOp2 =      vpOp1;
;
    op2 = vpOp2;
    ov = ~ov;
  end
end
endmodule

module I25_c(
op1, op2, op3, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
input op2;
output op3;
input iv;
output ov;
wire [0:23] op1;
wire [0:23] op2;
reg [0:23] op3;
reg ov;
wire iv;
VpDescriptor d1;
VpReg [0:23] vpOp1;
VpReg [0:23] vpOp2;
VpReg [0:23] vpOp3;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp1, d1);
  $VpAssocDescrToData(vpOp2, d1);
  $VpAssocDescrToData(vpOp3, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $VpCopyReg2Vp(op1);
    vpOp2 = $VpCopyReg2Vp(op2);
    vpOp3 = vpOp1 + vpOp2;
    op3 = vpOp3;
    ov = ~ov;
  end
end
endmodule

module I26_c(
op1, op2, op3, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
input op2;
output op3;
input iv;
output ov;
wire [0:23] op1;
wire [0:23] op2;
reg [0:23] op3;
reg ov;
wire iv;
VpDescriptor d1;
VpReg [0:23] vpOp1;
VpReg [0:23] vpOp2;
VpReg [0:23] vpOp3;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp1, d1);
  $VpAssocDescrToData(vpOp2, d1);
  $VpAssocDescrToData(vpOp3, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $VpCopyReg2Vp(op1);
    vpOp2 = $VpCopyReg2Vp(op2);
    vpOp3 = vpOp1 - vpOp2;
    op3 = vpOp3;
    ov = ~ov;
  end
end
endmodule

module I27_c(
op1, op2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
output op2;
input iv;
output ov;
wire [0:23] op1;
reg [0:23] op2;
reg ov;
wire iv;
VpDescriptor d1;
VpReg [0:23] vpOp1;
VpReg [0:23] vpOp2;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp1, d1);
  $VpAssocDescrToData(vpOp2, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $VpCopyReg2Vp(op1);
    vpOp2 =      vpOp1;
;
    op2 = vpOp2;
    ov = ~ov;
  end
end
endmodule

module I28_c(
op1, op2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
output op2;
input iv;
output ov;
wire [0:23] op1;
reg [0:23] op2;
reg ov;
wire iv;
VpDescriptor d1;
VpReg [0:23] vpOp1;
VpReg [0:23] vpOp2;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp1, d1);
  $VpAssocDescrToData(vpOp2, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $VpCopyReg2Vp(op1);
    vpOp2 =      vpOp1;
;
    op2 = vpOp2;
    ov = ~ov;
  end
end
endmodule

module I29_c(
op1, op2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
output op2;
input iv;
output ov;
wire [0:23] op1;
reg [0:23] op2;
reg ov;
wire iv;
VpDescriptor d1;
VpReg [0:23] vpOp1;
VpReg [0:23] vpOp2;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp1, d1);
  $VpAssocDescrToData(vpOp2, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $VpCopyReg2Vp(op1);
    vpOp2 =      vpOp1;
;
    op2 = vpOp2;
    ov = ~ov;
  end
end
endmodule

module I30_c(
op1, op2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
output op2;
input iv;
output ov;
wire [0:23] op1;
reg [0:63] op2;
reg ov;
wire iv;
VpDescriptor d1;
VpReg [0:23] vpOp1;
real vpOp2;
initial begin
  $VpSetDescriptorInfo(d1, 9, 15, `TWOS_COMPLEMENT, `TO_NEAREST_INTEGER_IF_TIE_TO_MINUS_INF, `SATURATION+`WARNING, 1);
  $VpAssocDescrToData(vpOp1, d1);
  ov = 1'b0;
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp1 = $VpCopyReg2Vp(op1);
    vpOp2 =      vpOp1;
;
    op2 = $realtobits(vpOp2);
    ov = ~ov;
  end
end
endmodule

module I31_c(
address1, address2, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
output address1;
output address2;
input iv;
output ov;
reg [0:63] address1;
reg [0:63] address2;
reg ov;
wire iv;
VpFCartesian vpOp1;
VpFPolar vpOp2;
initial begin
  ov = 1'b0;
  address1 = $VpAddress(vpOp1);
  address2 = $VpAddress(vpOp2);
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp2 =      vpOp1;
;
    ov = ~ov;
  end
end
endmodule

module I32_c(
op1, op2, op3, op4, op5, op6, op7, op8, address9, op10, iv, ov);
`include "finsimmath.h"
`include "finparam.h"
input op1;
input op2;
input op3;
input op4;
input op5;
input op6;
input op7;
input op8;
output address9;
input op10;
input iv;
output ov;
wire [0:175] op1;
wire [0:31] op2;
wire [0:63] op3;
wire [0:63] op4;
wire [0:119] op5;
wire [0:79] op6;
wire [0:31] op7;
wire [0:31] op8;
reg [0:63] address9;
wire [0:79] op10;
reg ov;
wire iv;
integer vpOp2;
real vpOp3;
integer vpOp7;
integer vpOp8;
real vpOp9 [0:2][0:1023];
initial begin
  ov = 1'b0;
  address9 = $VpAddress(vpOp9);
end

always @(iv) begin
  if (iv === 1'b1 || iv === 1'b0) begin
    vpOp2 = op2;
    vpOp3 = $bitstoreal(op3);
    vpOp7 = op7;
    vpOp8 = op8;
$Flot("Spectrum_detailed.html", vpOp2
, vpOp3
, "Spectrum", "frequency (GHz)", "Amplitude ", vpOp7
, vpOp8
, vpOp9
, "inSpectrum");
    ov = ~ov;
  end
end
endmodule

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