2.1 Super-FinSim directory structure 2
2.2 Super-FinSim installation guide 2
2.2.1 Installing the UNIX distribution 2
3.1 Operations performed by the compiler 8
3.2 Invoking the Verilog Compiler 8
3.2.1 Verilog Compiler Options 9
3.2.2 Precedence order for simulation mode options 19
3.3 Files generated by the Verilog compiler finvc 19
3.4 Incremental recompilation 19
3.5.1 Compiling a Verilog Design Hierarchy into object code for later reuse 20
3.5.2 Using a separately compiled hierarchy 21
3.6 Calling user C tasks/functions in Super-FinSim without the PLI interface 22
3.7 Using Mixed Verilog/SysytemC descriptions 23
3.7.1 3.7.2 Instantiating SystemC modules in Verilog 23
3.7.2 3.7.3 Invoking finvc when there are SystemC modules involved 23
3.7.3 3.7.4 Rules to be observed by SystemC modules instantiated in Verilog: 23
3.7.4 3.7.5 Invoking TOP.sim or the name of the simulator 24
4.1 Operations performed by the simulation builder 24
4.2 Invoking the simulation builder 25
5.1 Using the Fintronic PLI table 27
5.1.1 Creating the table manually 28
5.1.2 Creating the table automatically 29
5.2 Building a custom compiler 30
6.1 Operations performed by the simulation engine 32
6.4.2 Interactive Simulation 35
6.4.4 The Save and Restart feature in Super-FinSim. 36
6.5 Starting a real time waveform display 38
7.1 List of interactive commands 40
7.2 Processing simulation data structures 43
7.4 Handling of simulation scope 44
7.5 Querying of simulation objects 45
7.6 Super-FinSim environment variables 46
7.7 Miscellaneous system facilities 47
8.2 Variable Precision Fixed Point and Floating Point Support in Super-FinSim 50
8.5.2 Setting the fields of the descriptor 53
8.5.3 The Default Descriptor 55
8.6 VP register manipulation 55
8.6.1 Simple Assignments toVP registers 55
8.6.2 Arithmetic Operators operating on VP registers 57
8.6.3 Logical Operators involving VP registers 59
8.6.4 Assignments to non-VP objects 59
8.6.5 Trigonometric Direct and Inverse Functions 59
8.6.6 Hyperbolic direct and Inverse Functions 60
8.6.7 Functions returning universal constants 61
8.6.8 Logarithm and Exponential Functions 61
8.6.9 Other Functions accepting VP registers as operators 62
8.6.10 Using Special Condition Signals/Flags of VP registers 63
8.6.11 Assigning VP registers to verilog registers 63
8.6.12 Assigning verilog registers to VP registers 64
8.6.13 Assigning Verilog Real to Verilog registers 64
8.6.14 Displaying VP register values 65
8.7 Cartesian and Polar types 67
8.7.5 Operators on Cartesian and Polar types 68
8.8 Operations on Multi-dimensional arrays 69
8.8.1 Populating Multi-dimensional arrays with values 69
8.8.2 Viewing elements of a multi-dimensional array as part of a different structure 71
8.8.3 Displaying Multi-dimensional Arrays 71
8.8.6 Fast Fourier Transform: $VpFft and $VpIfft 75
8.8.7 Discreete Cosine Transform: $VpDct and $VpIdct 75
8.8.8 Linear Differential Equations 76
8.8.9 Numeric Differentiation and Integration 77
8.8.10 Symbolic Computation 78
9.1 Running Super-FinSim in pure interpreted mode 84
9.2 Running Super-FinSim in mixed mode 84
10.1 Super-FinSim status codes and errors 88
11.2 Code Coverage Information 90
12.1 Running Super-FinSim with Specman 92
12.1.1 Verilog Compilation. 92
12.1.2 Building the simulator. 92
12.1.3 Running the simulation. 93