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Support for Verilog 2001

Third party tools integrated with FinSim

Fintronic Announces FinFilter, that generates FIR Filters in gate-level Verilog and the associated test bench in mixed Verilog/FinSimMath.

    Business Editors/High-Tech Writers

San Mateo, Calif.--10:00am PST, Monday May 28th, 2012--

Fintronic USA, Inc., a leading provider of high-performance Verilog simulators announced support for FinFilter, a generator of gate-level Verilog descriptions of FIR filters, which also generates an associated test bench in mixed Verilog/FinSimMath.

David Coelho, founder of Vantage Analysis Systems, maker of the first commercial VHDL simulator and author of the first book on VHDL stated: "FinSimMath brings in one language the mathematical and RTL levels of abstraction in the same way in which VHDL and Verilog brought in one language RTL and gate levels, creating the potential for a huge increase in the productivity of designers".

Dr. Alec Stanculescu, CEO and President of Fintronic USA, stated "FinFilter is an IP generator producing mixed Verilog/FinSimMath. Its usage brings a huge productivity increase due to: 1) fast simulation, since it is performed mostly at the mathematical level, 2) easy pluggin of gate-level models for detailed simulations due to the fact that the interfaces of modules are described using pure Verilog, and 3) a test bench that uses mixed FinSimMath/Verilog assertions. An example of the high design productivity that comes from using FinSimMath is that within seconds one can see the impact of truncating coefficients on both the implementation cost and on the quality of the filtering".

     About FinFilter

A formal description of FinFilter is provided in the last section of chapter 8 of the FinSim User's Guide, available for download on www.fintronic.com/support.html. More information on FinFilter is available at www.fintronic.com/finfilter.html.
FinFilter generates FIR filters as structural-level Verilog descriptions. For constant coefficients FinFilter generates an optimized network of adders that produces an output at each clock cycle. In case the sampling rate is higher than the rate of the internal clock, FinFilter generates more than one filtering unit, all working simultaneously. In case the output rate is smaller than the sampling rate some of the simultaneous filtering units are omitted.
FinFilter also generates the associated test bench that includes an input generator, code using mixed FinSimMath/Verilog to check the correctness of the results, code to create the graphical representation of the amplitude response, i/o spectrum and i/o signals, code that models the channeling of the sampled data to the input of the filter (performing deserialization/serialization as needed), bit accurate functional models of the resources used (e.g. adders, delays, etc.), as well as the computation of the distance between the ideal output and the output produced by the filter.
The generated filter can be simulated very fast since it uses resources modeled at the functional level, and at the same time one can easily replace a few resources with their gate-level models because the ports are at the Verilog bit level.
It is the combination of fast and accurate software simulations of the generated filter, the availability of the corresponding mathematical computation of the amplitude response and i/o spectrum and the highly optimized implementation of the generated filter that makes FinFilter an IP generator that takes full advantage of the capabilities of FinSimMath.

     Getting a FinFilter License
For getting a FinFilter License please send your request to sales@fintronic.com.
     About Fintronic USA
Fintronic USA, Inc. is a technology leader in high-performance Verilog Simulation, as well as mixed Verilog/FinSimMath simulations. Fintronic has sold the first Verilog simulator on Linux in 1993. The company is committed to develop and deliver high performance simulators and IP Generators that provide a huge productivity increase in designing very complex electronic systems.

For more information on Fintronic USA, Inc. and its products, visit (www.fintronic.com), contact Dr Alec Stanculescu at (415) 265 5046, or send e-mail to info@fintronic.com.

Note to Editors: FinSim is a registered trademark of Fintronic USA. All other brand or product names may be trademarks or registered trademarks of their respective companies and should be treated as such.

		What is new @ Fintronic ?

About Fintronic What's new at Fintronic What our customers are saying... Support for Verilog 2001 Third party tools integrated with FinSim		Fintronic Announces FinFilter, that generates FIR Filters in gate-level Verilog and the associated test bench in mixed Verilog/FinSimMath. Business Editors/High-Tech Writers San Mateo, Calif.--10:00am PST, Monday May 28th, 2012-- Fintronic USA, Inc., a leading provider of high-performance Verilog simulators announced support for FinFilter, a generator of gate-level Verilog descriptions of FIR filters, which also generates an associated test bench in mixed Verilog/FinSimMath. David Coelho, founder of Vantage Analysis Systems, maker of the first commercial VHDL simulator and author of the first book on VHDL stated: "FinSimMath brings in one language the mathematical and RTL levels of abstraction in the same way in which VHDL and Verilog brought in one language RTL and gate levels, creating the potential for a huge increase in the productivity of designers". Dr. Alec Stanculescu, CEO and President of Fintronic USA, stated "FinFilter is an IP generator producing mixed Verilog/FinSimMath. Its usage brings a huge productivity increase due to: 1) fast simulation, since it is performed mostly at the mathematical level, 2) easy pluggin of gate-level models for detailed simulations due to the fact that the interfaces of modules are described using pure Verilog, and 3) a test bench that uses mixed FinSimMath/Verilog assertions. An example of the high design productivity that comes from using FinSimMath is that within seconds one can see the impact of truncating coefficients on both the implementation cost and on the quality of the filtering". About FinFilter A formal description of FinFilter is provided in the last section of chapter 8 of the FinSim User's Guide, available for download on www.fintronic.com/support.html. More information on FinFilter is available at www.fintronic.com/finfilter.html. FinFilter generates FIR filters as structural-level Verilog descriptions. For constant coefficients FinFilter generates an optimized network of adders that produces an output at each clock cycle. In case the sampling rate is higher than the rate of the internal clock, FinFilter generates more than one filtering unit, all working simultaneously. In case the output rate is smaller than the sampling rate some of the simultaneous filtering units are omitted. FinFilter also generates the associated test bench that includes an input generator, code using mixed FinSimMath/Verilog to check the correctness of the results, code to create the graphical representation of the amplitude response, i/o spectrum and i/o signals, code that models the channeling of the sampled data to the input of the filter (performing deserialization/serialization as needed), bit accurate functional models of the resources used (e.g. adders, delays, etc.), as well as the computation of the distance between the ideal output and the output produced by the filter. The generated filter can be simulated very fast since it uses resources modeled at the functional level, and at the same time one can easily replace a few resources with their gate-level models because the ports are at the Verilog bit level. It is the combination of fast and accurate software simulations of the generated filter, the availability of the corresponding mathematical computation of the amplitude response and i/o spectrum and the highly optimized implementation of the generated filter that makes FinFilter an IP generator that takes full advantage of the capabilities of FinSimMath. Getting a FinFilter License For getting a FinFilter License please send your request to sales@fintronic.com. About Fintronic USA Fintronic USA, Inc. is a technology leader in high-performance Verilog Simulation, as well as mixed Verilog/FinSimMath simulations. Fintronic has sold the first Verilog simulator on Linux in 1993. The company is committed to develop and deliver high performance simulators and IP Generators that provide a huge productivity increase in designing very complex electronic systems. For more information on Fintronic USA, Inc. and its products, visit (www.fintronic.com), contact Dr Alec Stanculescu at (415) 265 5046, or send e-mail to info@fintronic.com. Note to Editors: FinSim is a registered trademark of Fintronic USA. All other brand or product names may be trademarks or registered trademarks of their respective companies and should be treated as such.