Fintronic USA Inc. is a provider of high performance Electronic
Design Automation (EDA) tools. These tools are crucial for the
design of digital circuits. The first step in the design of a digital circuit is to
formally describe the desired functionality of the circuit in a
Hardware Design Language, such as Verilog HDL. This description of the
circuit is used as input to a simulator which will enable the designer
to find out whether the described circuit is indeed what is needed. If
not, the specification (in the form of the Verilog description) is
modified until it becomes acceptable. Once satisfied with the functionality,
the designer refines and details this description to
lower levels of abstraction (the "register transfer level" and the "gate level"), with the
ultimate goal of creating a very simple description of the circuit which can then be sent
to the fabrication facilities where the actual silicon chips are produced. During this
process of refining the description of the design, the design engineer has to continue
to simulate the circuit to ensure that the original functionality is still maintained.
Given the increased complexity of modern day chips and the critical importance of
market timing, the electronics industry is craving for increased
verification throughput which can reduce the turnaround time of the
design cycles. Fintronic USA addresses these issues by providing
Super FinSim, which is one of the most accurate and fast Verilog
simulators in the industry.
Along with its Verilog simulators Fintronic USA provides other related EDA tools
helping the design engineer during the design cycle such as:
- support for FinSimMath, a superset of Verilog that supports mathematical descriptions
- FinFilter, an FIR filter generator that generates the gate-level filter representation in Verilog as well as an associated testbench written in FinSimMath
- FinCov, a code coverage tool that provides the user with feedback regarding the quality of the test vectors used to verify the digital circuit, by reporting how many times each line is executed.
- FinVA allows users to syntactically and semantically verify a Verilog description and create an attributed intermediate format which can be used in conjunction with the FinVFI package to create any tool for Verilog analysis/synthesis/verification.
FinSimMathTM provides the following advantages:
1) supports transformation in small steps from math-level to Verilog RTL or C/C++ for easy debugging.
2) bit-accurate models and optimization of formats and sizes comes with little effort, due to patented technology which allows the specification and modification of formats and sizes of operands during the simulation.
3) exception management is supported by having implicit "overflow" and "underflow" registers associated with variable precision data containers.
Super-FinSim is Fintronic's top performance, fully compliant Verilog simulator. It
supports PLI 1.0, SDF, VCD, SystemC, FinSimMath and provides through integration with third
party source level debuggers, waveform displays etc. a complete simulation environment on
all popular platforms. FinSim provides the flexibility of mixed compiled and interpreted
simulation and an efficient incremental compilation.
Fintronic has a mission to supply the highest performance Verilog HDL simulators
available for full language design verification and timing simulation. It is privately
held and privately funded.